Hello all. Sorry, been a while since I've been around.

I'm designing a circuit around the ATF1508ASV CPLD chip.
Specifically: https://www.mouser.com/ProductDetail/55 ... SV15AU100T (TQFP-100)

In the datasheet, it briefly mentions pins 88 and 90. Which are the "INPUT/OE1" and "INPUT/OE2/GCLK2" pins respectively.

I sort of understand that pin 90 (GLCK2) is one of the three global clocks and can be used with an external clock.
But what is OE1 for? For that matter, when would OE2 be utilized as well?

I've searched through the datasheet and I must be missing something. I see them referred to as "Global OE" pins. I also see them mentioned in a block diagram but I'm missing the information what they actually are and when/how to utilize them.

Sorry for such a newbie question but I'm just now getting back into learning CPLD's.

Any information would be appreciated.

Thanks!

_________________
Cat; the other white meat.

The 4 input-only lines, reset, clock1, clock2, and output-enable are optimized for their respective functions of reset, clock and output enable, but they can also used as general-purpose inputs. You definitely should use clock inputs as clock for the internal flip flops to minimize skew; and board reset should connect to the CPLD reset input. Output enable is less useful and I generally reuse it as general inputs.
Bill

For most purposes, it's probably a nicety. But, much as using GLCEAR is most efficient for a widely-used clear, it might be best, if you have one or two banks of bidirectional I/Os, to use the OE1 and OE2 signals to control them. (If not needing to derive your OEs in the logic...)

From the datasheet:


The internal architecture is - to me - interesting, and if trying to make the very best use of a CPLD, is probably useful too. There are good diagrams in the datasheet.

Thanks for the responses! That makes sense. I was hoping that it wasn't behaving like an /OE pin on an SRAM chip.

_________________
Cat; the other white meat.

Each Macro Cell has five product terms. Each PT can be combined with other PTs and then routed to any function of the OMC. E.g you can route the result of the equation to the .ck or the .oe function of the OMC. However whenever you do so you use one of the five PTs and therefore you have less PTs available for other combinatorial logic used for the OMC to control the .d input of the FF or to generate the logic for the output itself.

However when you use one of the special input pins CLK1, CLK2, CLK3, OE1, OE2 and CLR you can route them directly to the .ck, .oe, .ar function of the OMC without using one of the PT. Therefore it is always clever to use these pins for these functions when it makes sense as this will free resources of every OMC that makes use of these inputs. Also in most cases the fitter will have less problems to fit a design as it has more choices to distribute the internal equations to the internal OMCs that are not connected to a PIN.

Also these signal do not count as FAN-In of a OMC Blocks. FAN-IN is the number of input signals that can be used in one block of 8 OMCs, the maximum FAN-IN of an ATF OMC block is 40.

Another point is, that you can only use the .ce (Clock Enable) function of a registered OMC if the .ck is one of the global CLK signals.

Of course you can borrow PTs from a neighboring OMC but this makes the OMC useless as it no longer can be used to create an output.

For example using a global OE allows you to define a 5 to 1 MUX using only the 5 PT of a single OMC and still be able to control the output direction of this pin