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x86?  We ain't got no x86.  We don't NEED no stinking x86!

If you raise a topic on the 6502 forum, it either dies or it gets investigated thoroughly. In this case, it is investigated thoroughly.

I've been following Agumander's GameTank console with dual port RAM to a 6502 audio co-processor. I've also investigated clock stretching circuits which allow two or more cores to synchronously access shared pools of memory and therefore side-step the requirement for dual port RAM.

It is relatively easy to get two cores running at 40MHz. The trick is to use two tiers of clock stretching. Contrary to popular belief, it is also relatively easy to exceed two cores. Admittedly, there are barriers at every power of two; starting from mono core to dual core. However, they are surmountable. Unfortunately, large clusters of synchronous cores are more suited to computation. If you want an ad hoc number of cores or, in the case of multi-media, you want homogenous cores to perform heterogenous I/O tasks, systems with dual port RAM offer the most flexible timing.

In the trivial case, a star network of dual port memory allows one processor to conduct video cards, audio cards and secondary processors. A tree of processors or more general arrangement is also possible. To avoid one or more processors having a memory map full of dual ports, it is possible to bank switch such that all ports always appear in the same address range on all cores. In the case of a tree structure, all up-stream and down-stream ports may have common addresses.

Unfortunately, a parallel bus with eight or more addressable dual port RAM interfaces may be restricted to 2MHz or so. This can be moderately improved by dividing a bus into two or more segments, for example, by placing the root of the tree in the middle of the main bus.

If the main bus does not have DMA then transfer from storage to audio output may be less than 140KB/s. This is insufficient to play uncompressed CD audio. With DMA, it is possible to play audio and video across multiple screens in addition to other functionality. (Unfortunately, video quality may be 40% worse than MJPEG.)

Finally, some of the regulars are being very modest. I presume this to not stomp on people's ambitions.



Dr Jefyll is one of the world's most prominent practitioners of chip stacking. This improbable field is divided into memory stacking, logic stacking and processor stacking. Radical Brad has some beautiful photography of RAM stacking and Dr Jefyll is the inventor of the LE74HC574K245N. GARTHWILSON is also quite good in this field. I merely wrote about processor stacking after discovering the bogosity of Rockwell's vaporware dual core 6502. However, I have zero practical experience with chip stacking.



I specifically use a chequerboard analogy in Grid Computing With 6502, 65816 And/Or 65265, a topic which has an embarrassingly similar diagram to BigEd's Multiprocessing on FPGA using dual-port RAM (pipedream).

Regardless, it is easier to boot a star or tree of cores via dual port RAM. It is easier to connect them to unrelated I/O via dual port RAM. And Agumander has a good example running.

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Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!

(Oh, yes, I see now you did mention chequerboard - oops!)

BigEd, after investigation, I find that our synchronous and asynchronous designs are entirely compatible and yet possibly moot. It is possible to lash together 2-16 cores with a synchronous clock and then scale such clusters significantly further with the use of dual port RAM. However, it may be cheaper and more practical to use clock stretching, SPI and FPGA to make Transputer links. Indeed, it may be possible and desirable to make such links binary compatible with Transputers. Either way, autonomous serial links may be the preferred arrangement for us and others.

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Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!

My future self sends reversed time's arrow thanks you for this post. My current self is still reading up on basics of high speed circuit design. Haha!