When booting the 6502, there must be RAM in $00-$FF. And there should be also RAM in $100-$1FF for programs work reliably. (*)

And there should be somethingthat the CPU could read in $FFF0-$FFFF. Either ROM, or RAM with the appropiate locations filled with values, put there before kickstarting the CPU.

I was wondering about having the 6502 access the first 32K of memory as fixed RAM, and then bank the other 32K with the flip of a switch.

The fixed RAM would be where the main code of an app, game or OS would be. There would be also mapped inside access to things like storage and different chips like serial or parallel ports, sound and graphics, through the use of registers that would be inside those first 32K.

And the following memory from 32K up to 64K would be swappable, and would contain data that the code running in the first 32K could use. Or even more code that wouldn't be running all the time but only when needed.

What would be that chip that would allow for a redirection of the top 32K? Some kind of memory selector?

It seems at first that a 74x15x chip would do it. Well... actually a bunch of them!

You don't need much, I think: the large RAM chip which is mapped into the top half just needs to get its high address bits from a register which is writeable as I/O. So, an 8 bit latch is enough: a '273 perhaps.
https://mil.ufl.edu/3701/pinouts/74200.html

As you note, for this scheme you need I/O in the low half - page 2 might be attractive.

Let's make it the '70s way:

• A 74HC251 uses three S inputs to select one of its eight D inputs, to be redirected to it Y output.
  Eight '251 chips and a 256Kx8 SRAM chip could be used to have eight banks of 32K RAM.
  
  
• A 74HC253 uses two S inputs to select one of its four 1D/2D inputs, to be redirected to its corresponding Y1/Y2 outputs.
  Four '253 chips and a 128Kx8 SRAM chip could be used to have four banks of 32K RAM.

But the thing is that the S inputs are not static, so a latch should be put before them, to have them set all the time until changed by the CPU.

Another thing is that the change of bank should be done before the CPU trying to read the memory from the selected bank, so it should be done during the half cycle the CPU is not accessing the bus.

Am I over engineering this?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I think this is over-complex...

You'd need an array of registers for the high bits, if you planned to map in multiple sections from the big RAM - for example, mapping 8k pages on 8k boundaries. And yes, you need to pick the right register to read from on each access.

But your original sketch was to have only one active mapping, into a 32k area, and for that you only need one register. Well, so long as 8 extra bits of address is enough.

In fact the BBC Micro has such a simple system: there's a 16k window where one of 16 memories can be mapped in. So there's a 4 bit latch/register, which is written when the program needs to change from one memory to another.

(My feeling is that discussions of this type of question can get confused if the word 'bank' or 'page' or 'slot' is used loosely or used for more than one thing. But I haven't settled on a terminology.)

I think I didn't understand how to approach this.

A0-A14 are the lines used by the 6502 to address its first 32K of memory.

Once I turn A15 on, that falls into the second 32K of memory. A15 would be used as chip select for a second 32K chip. That second 32K chip would be a virtual one, and by virtual I'm saying one of the 32K banks or sections of memory inside a larger chip. A 256K chip has 8 of that sections. To select one of those sections, I would enable the address lines above A14 in the 256K chip accordingly. But to its eyes, the 6502 is just accessing memory that falls between $8000 and $FFFF.

That enabling should be made by writing a four bits register. That register would be a latch or flip-flop chip that would be kept static that until reset or changed by the CPU. Those four bits should be maped in location that would fall in the first 32K bank of memory, and should be changed only when the program counter would be pointing to an address =<$7FFF, unless extreme careful programming would allow for switching banks and having code there that would continue running with no problems.

For every extra bit used, the addressable memory is doubled, and the amount of banks of high 32K of memory is doubled.

Right until here?

Well... the 65C816 has its own way of doing things, as it wouldn't need no banking at all, unless more than 16MB would be wanted to be used, isn't it?

Edit: typos

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Is there any way, BDD, to have a discussion about banking on the 6502 without getting diverted into a discussion of the '816?

I would have hoped that the thread title and first post would set up the context for the discussion, and it might be true for almost everyone here, but somehow it's not quite enough for everyone.

Back to the topic of the thread:

> That enabling should be made by writing a four bits register. That register would be a latch or flip-flop chip that would be kept static that until reset or changed by the CPU. Those four bits should be maped in location that would fall in the first 32K bank of memory, and should be changed only when the program counter would be pointing to an address =<$7FFF, unless extreme careful programming would allow for switching banks and having code there that would continue running with no problems.

Yes, this is all sounding good so far, until you mention checking the program counter. That bit I don't quite understand.

Why did you mention PC < $8000? Were you thinking of that as distinguishing the first instruction of the application running? (In fact, what you do is check the address bus in a Sync cycle.) That's a reasonable thing to do: you enable the large memory when you're running in low memory. But you're not changing the 4 bit value, you're switching in that mechanism and switching out a different mapping which doesn't even include the large RAM.

After reset, after getting your program loaded, the 4 bits which control the upper bits of the large RAM will be updated whenever the program chooses to write to the appropriate I/O location, and not at any other time.

That is, there are two kinds of mapping being done, or from the point of view of the 6502's address map, two kinds of substitution. One is about accessing a large RAM, and the other is about where post-boot code and data comes from.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The banking system I'm thinking about works by replacing the whole high 32K area everytime a bank is switched out.

What the 6502 would be seeing is the low 32K being always the same. And the high 32K would change completely when the bank registers are changed.

So: if PC <$8000, then no matter how many times the high 32K changes, the next instruction to be processed would be the expected one.

But if PC >=$8000, and the code there changes the bank, then the next instruction wouldn't be the expected one because all what is contained in $8000-$FFFF in different from what was there previously...

...unless what is stored in the new bank is the right instruction to be processed, because that's how it was coded.