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PostPosted: Wed Apr 28, 2021 4:21 pm 
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I've been looking around for a device to generate a variable-speed clock.

10 years ago Garth was kind enough to post a VFO circuit with '7-bits' of switchable capacitors http://forum.6502.org/viewtopic.php?f=1&t=2013&p=17478#p17478.

Recently I found a flood of Si5315A-based devices with PLLs settable between 8KHz and 160MHz that are sold as boards for under US$10. All of them seem similar, with 3 outputs and I2C controls. They are available from https://www.adafruit.com/product/2045 and any number of resellers, as well as Aliexpress and Amazon. The price is close enough to the cost of a single-frequency oscillator, but I don't think there is any way to keep a frequency setting on the device without programmining it after a powerup, making it not feasible as a main clock.

A minor snag: the output seems to be 3.3V - which may be what you want anyway. I am sticking to 5V for my current projects, so I would think the usual 74HC74 divide-by-two flip-flop should remedy that. Am I correct that 5V HC logic would work with 3.3V peak-to-peak square-wave input?

Has anyone used these? I'd love to hear about your experiences. I am somewhat put off by the Adafruit tutorial as it requires an Arduino with a whole lot of magic clicking in the IDE or Circuit-Python libraries (don't get me started...) But I might even go through with that torture, if I can't find a C library for Raspberry Pi's i2c pins or something of that sort.

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PostPosted: Wed Apr 28, 2021 6:00 pm 
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enso wrote:
I don't think there is any way to keep a frequency setting on the device without programmining it after a powerup, making it not feasible as a main clock.
Is the default frequency upon powerup lower than what you desire? If so, maybe you can tolerate running at the lower frequency until the system wakes up sufficiently to set the oscillator to the desired frequency.

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Am I correct that 5V HC logic would work with 3.3V peak-to-peak square-wave input?
It might work, but HCT would be a much better choice. :)

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PostPosted: Wed Apr 28, 2021 6:04 pm 
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enso wrote:
10 years ago Garth was kind enough to post a VFO circuit with '7-bits' of switchable capacitors http://forum.6502.org/viewtopic.php?f=1&t=2013&p=17478#p17478.

Note that the switchable capacitors just set the range, but there's a trimmer resistor that sets the actual frequency within that range. (IOW, it's infinitely variable.) The faster one is at viewtopic.php?p=10619#p10619 .

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A minor snag: the output seems to be 3.3V - which may be what you want anyway. I am sticking to 5V for my current projects, so I would think the usual 74HC74 divide-by-two flip-flop should remedy that. Am I correct that 5V HC logic would work with 3.3V peak-to-peak square-wave input?

You want 74HCT, or 3X the speed, 74ACT, not 74HC or 74AC. The "T" means TTL-level inputs, meaning anything above 2V is considered a '1'.

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PostPosted: Thu Apr 29, 2021 5:18 am 
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Dr Jefyll wrote:
enso wrote:
Am I correct that 5V HC logic would work with 3.3V peak-to-peak square-wave input?

It might work, but HCT would be a much better choice. :)

...and ACT would be even better. Edge rates for HCT logic's output are a tad slow for the Ø2 input to a WDC 65C02.

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PostPosted: Sat May 01, 2021 2:46 am 
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enso wrote:
I've been looking around for a device to generate a variable-speed clock.

Have you considered using a microcontroller? Many PIC microcontrollers include a 20-bit NCO (with 20-bit increment register) for frequency generation. Here are a few concepts I've thought about;


Attachments:
K8LH Clock 001.png
K8LH Clock 001.png [ 74.73 KiB | Viewed 1404 times ]
K8LH Clock 002.png
K8LH Clock 002.png [ 112.72 KiB | Viewed 1406 times ]
Klock.png
Klock.png [ 75.23 KiB | Viewed 1406 times ]


Last edited by Michael on Sat May 01, 2021 10:23 am, edited 1 time in total.
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PostPosted: Sat May 01, 2021 6:36 am 
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The 8-pin PIC sounds kind of promising - how hard could it be?

Funny, I just spent (wasted, really) some time with an ESP32, again. It always seems so tempting to hack it apart, but in practice I spent over an hour trying to install the environment that has to be around half a gigabyte, with all the joys of doing it twice for stupid unresolvable dependency issues on my aging machine. In the end I installed it and watched it do its thing for about 15 minutes, and then it turned out that there is a whole other pile of crap it needed to download and compile. Scary looking python warnings flashing. With lots of stopping to get some or other package that is missing. Finally I got the compiler, and spent a lot of time trying to find something simple and not completely out of date on the internet. I knew it was a bad idea, but now I was really invested, and it supposedly can generate up to 80MHz square wave with the PLL and synthesizer with incomprehensible layers of settings and divisors, and volumes of documentation.

Finally got 'hello' world to compile... They've got to be kidding - it takes like 5 minutes to compile! There is a counter that literally went from 1 to 100 as it ground my remaining spinning drives. And I've never seen that much documentation for anything other than a mainframe - not exaggerating. And it feels like mainframe - there is deep magic in the box, and you are just not smart enough to actually grok the whole thing, or even figure out its components stuck into the chip-sized package. It is amazing - it can do anything, any protocol imaginable, and even has a fallback into BASIC someone stuck inside a some forgotten internal ROM. It's also pretty much impossible to do anything - at least I just don't have the patience to study the poorly written and often marketing-obfuscated manuals with incomprehensible translations for the more tricky parts.

I finally gave up in this combination of awe and disgust. Again. I tried to clean up the drives, and found hundreds of megabytes hidden in some .local directory (or something like that) some from the last time I tried this. I am annoyed with myself as I can't possibly trust the computer after this excersize in loading scary software from some Chinese guys...

So, let's say it's wonderful, as I don't want to be a grouch.

P.S. Not entirely true. With some effort, you too can blink some LEDs, and even connect to your WiFi network and then blink some LEDs.

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PostPosted: Sat May 01, 2021 12:26 pm 
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I do like the idea of these PIC clock generators! Configuring by serial input is nice, as it's both input and display, and ideal for debugging. Three cases spring to mind: pushing the speed up or down by small increments to troubleshoot the max speed of something; setting one of a small number of preferred operating frequencies; and running a board at +10% or +5% to gain confidence that there's some margin.

At present in the beeb816 project Dave and Rich are swapping crystals and selecting small divisors to explore frequencies in the range 8 or 12MHz to 16MHz. Being able to set the speed from a serial line sounds like an improvement.


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PostPosted: Wed May 05, 2021 7:35 am 
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Ugh. The manual for PIC16F15313 is over 500 pages, of course. I've used PICs on a couple of occasions and have a PICIT somewhere. The newer PICs are not as terrible as the old PIC12s, and the goal here would be to lock the PLL and configure an external clock pin, which should not require any runtime software. Handling input from a DIP switch or an encoder is pretty contained... I can see doing a 'hit-and-run' PIC project without going too far up the a**...

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PostPosted: Wed May 05, 2021 8:09 am 
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Just to check something, Michael, about the PIC and the NCO and the clock that it can make. It is, presumably, the case that every edge on the output clock - the one whose frequency we aim to have in tight control - is placed on an active edge of some internal high speed clock, running perhaps at 40MHz.

In which case, we can place edges on a 25ns granularity, and so adjust the high and low clock phases on a 25ns granularity. That gives us certain natural output frequencies which will have no jitter, and if we set the NCO to produce any other frequency, we'll get the right average but we will have jitter from one phase to the next.

Is that the right picture?


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PostPosted: Wed May 05, 2021 9:03 am 
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That's correct, BigEd.

A 4.194304-MHz crystal (4xPLL) provides 8-Hz increments (up to approx. ~8-MHz).

An 8.388608-MHz crystal (4xPLL) provides 16-Hz increments (up to approx. ~16-MHz).

If you use the PIC 32-MHz Internal Oscillator you get 15.2587890625-Hz increments. For the case of generating a CPU clock, may I suggest using frequencies that are multiples of 15.625-kHz which will produce integer increment register values? For example;

inc_reg_value = int(8000000 / 15.2587890625) = int(524288.0 + 0.5) = 524288 'Fout = 8000000.0-Hz 0.000000%
inc_reg_value = int(8125000 / 15.2587890625) = int(532480.0 + 0.5) = 532480 'Fout = 8125000.0-Hz 0.000000%
inc_reg_value = int(8250000 / 15.2587890625) = int(540672.0 + 0.5) = 540672 'Fout = 8250000.0-Hz 0.000000%
...
inc_reg_value = int(8100000 / 15.2587890625) = int(530841.6 + 0.5) = 530842 'Fout = 8100006.1-Hz 0.000075%


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PostPosted: Wed May 05, 2021 9:58 am 
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Hmm, I need to do a little arithmetic. While this idea has its uses, I'm not sure it's suitable for what I was thinking of...

8.000000 MHz is a 125ns period
8.125000 MHz is a 123ns period
But, I think, we don't have a 2ns granularity of control on the placement of edges.

Let's suppose a 32MHz master clock, which has a period of 31.25ns. So four cycles of the master clock produces an exact 125ns period, which would be 8MHz exactly. (*) But the next even increment is to 3 cycles in one direction or 5 cycles in the other, which would be frequencies of approx 10.67MHz and exactly 6.40MHz.

I understand that the NCO produces a long-term average frequency that's pretty well controlled, and that might be very useful for radio or audio purposes, perhaps with filtering, but I'm struggling with the implications of clocking a computer this way: if one clock phase is 4 ticks long and the next is 3 ticks long, the computer will need to be fast enough to run at the 3 tick speed. We are adjusting the average speed of the computer, but we can't use this technique to explore the limits of speed.

Edit: in fact, perhaps, if we have a computer which can run at some speed which is an exact number of ticks per phase, then we can happily use the NCO technique to run at various lower average speeds. There might well be uses for that.

Am I still understanding correctly?

(*) actually a half-period, I think, which is 4MHz exactly.


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PostPosted: Wed May 05, 2021 10:32 am 
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Oh my goodness. I'm embarrassed. I've had an incorrect understanding all this time and I should have known better.

My apologies, BigEd. This scheme really isn't very useful except perhaps for generating ACIA clock frequencies which are usually divided by 16 or 64 in the ACIA chip.

Mike


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PostPosted: Wed May 05, 2021 11:02 am 
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No worries! Good to have dug in and figured it out. As you say, for clocking serial, that's very handy.


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PostPosted: Sat May 08, 2021 12:55 am 
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If I am following this correctly, sequential clock transitions are not spaced identically... Is the jitter limited to two sequential transitions? If so we could push them through a flipflop, effectively dividing the frequency by two and leveling the jitter. 40MHz (instead of 80) is sufficient for my purposes...

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PostPosted: Sat May 08, 2021 3:26 am 
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enso wrote:
If I am following this correctly, sequential clock transitions are not spaced identically... Is the jitter limited to two sequential transitions? If so we could push them through a flipflop, effectively dividing the frequency by two and leveling the jitter. 40MHz (instead of 80) is sufficient for my purposes...

No; because it's not just a matter of the duty cycle changing. If it's a numerically controlled oscillator (NCO), suppose, for the sake of illustration, and keeping it simple, that the phase accumulator is only 4 bits wide, able to hold values 0 through F, and we add 5 each time, and take only the high bit as our output.

  • The first line below shows the entire phase accumulator content after the "add 5" operation at each active edge of the input clock. (5 is just an example.)
  • The second line below shows the high bit which is used as output.
  • The third line below shows each rising edge of the output which you're thinking of putting into a flip-flop to divide it. As you can see, they're not evenly spaced.
  • The fourth line tells the number of ticks that the output's complete cycle takes, which is not consistent.
Code:
    0 5 A F 4 9 E 3 8 D 2 7 C 1 6 B 0 5 A F 4 9 E 3 8 D 2 7 C 1 6 B 0
    0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0
        |     |     |       |     |     |     |     |       |     |   
           3     3      4      3     3     3     3      4      3      3

5 was just the example input. The output's frequency will be proportional to the input number, ie, the number you add to the phase accumulator with every input clock active edge. If you were to clock the input at 16MHz, an input of 0 would give you DC, 1 would give you 1MHz, 2 would give you 2MHz, 3 would give you 3MHz, etc., up to 8 giving you 8MHz. (Beyond that, it will start aliasing.) Input numbers that cannot go evenly into 16 will produce jitter.

Here is is for 3:
Code:
    0 3 6 9 C F 2 5 8 B E 1 4 7 A D 0 3 6 9 C F 2 5 8 B E 1 4 7 A D 0
    0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0
          |         |           |         |         |           |
               5          6          5         5           6         5

The bigger input numbers will produce the more-serious jitter, in terms of the variability being a greater percentage of the output period. Here is is for 7:
Code:
    0 7 E 5 C 3 A 1 8 F 6 D 4 B 2 9 0 7 E 5 C 3 A 1 8 F 6 D 4 B 2 9 0
    0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
        |   |   |   |     |   |   |     |   |   |   |     |   |   |
          2   2   2    3    2   2    3    2   2   2    3    2   2   3

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