Don't implement this circuitry. It is a thought experiment to demonstrate that it is always possible to expand a system and that a formal edge connector is not required. It is inspired by BigDumbDinosaur's RTC to SCSI adaptor board. Initially, I thought this was a bodge but after working through the details, I find that it is best practice and certainly the most productive technique.
Many people want to design a computer system with maximum flexibility. In an attempt to avoid any obvious omissions, people may design an infinitely scalable system. This may involve a
vast number of processors but more often involves a vast number of peripheral expansion slots. Systems from the 1970s often had 4-8 parallel slots and there is a widespread but incorrect assumption that similar designs may run 30 times faster using contemporary parts. (This is correct for burst mode, sequential transfers but not random access.)
Knowledgeable experts make assurances that zero or one expansion cards are sufficient. This is often ignored and may contribute to projects being unnecessarily de-railed. They either do not advance beyond design or they encounter electro-magnetic problems. Raspberry Pi and Arduino are cited as examples where devices rarely, if ever, have more than one expansion. However, this is not a convincing argument; especially when such devices are used in multiples or twinned to combine their relative strengths. An analogous argument can be made about 6502. It does not have multiply hardware and is rarely used to perform intensive multiplication. That does not imply that intensive multiplication is superfluous. It only implies that 6502 does not fit this niche. Likewise, citing systems with limited expansion does not explain the existence of contrary systems.
BigDumbDinosaur successfully retro-fitted a clock socket as an I/O port for SCSI and subsequently obtained an informal world record for system uptime. Based upon this success,
I have advocated that a system with zero expansion slots may be expanded out from a ROM or RAM socket. The implication is that a system with no obvious expansion remains expandable - at least to the extent common among Raspberry Pi or Arduino. As a thought experiment, I have considered what is required to make an expansion connector suitable for 6502 (and possibly other processor architectures). The answer is: not very much. I began with a 28 pin, 15 bit address 27256/28256/62256 socket on the basis it is directly compatible with GARTHWILSON's minimal address decoding but also because devices of dubious provenance may be obtained for USD1 each.
I hoped to present the omitted signal lines in a DIP socket with a fixed offset from the 28 pin DIP socket. The first problem is the proximity of each socket to mechanical fixings. The second problem is the set of omitted signals. Most obviously is the omission of A15 from the 28 pin socket. Further address signals may be provided directly by 65816 or indirectly via 6502 and a strobe. (Indeed, BigDumbDinosaur regards 65816 $01xxxx viable for I/O.) It may also be desirable to provide RESET, raw clock, alt clock, slow decode and one or more interrupt signals. In all possible permutations, this never more than eight signals. Indeed, in typical applications, it is unlikely that more than three signal lines would be required. Therefore, it may be preferable to not group them into a socket but instead provide test points in the most convenient locations and then provide fly leads to anything sitting in the 28 pin socket.
Really? Really?? That's it?
Perhaps you are not convinced. I will investigate more formal options and demonstrate that they offer decreasingly poor value. I assume that you are designing an 100mm * 100mm board with 90mm * 90mm fixing holes. Placement of the 28 pin DIP socket and the 8 pin DIP socket is now tied to the board size in an effort to obtain mechanical compatibility. This doesn't waste too much board area until we consider I/O address decode. The base board probably has some I/O and unused strobes may be available via the 8 pin socket. Alternatively, redundant I/O decode (possibly with clashing addresses) may occur on the expansion board. If we want a super-duper design with 24 address lines, stackable cards and fully decoded address segments (which are rotated around, like
65SIB and other standards), I found that it is possible to place a 40 pin DIP socket and a 24 pin DIP socket between the fixing holes. This acts as a cheap keyed connector. In the trivial case, it also allows one end of the 40 pin DIP socket to be populated with 27256/28256/62256. The remainder of the 40 pin DIP provides redundant power/ground, RESET and A15-A23. Subsets of the 24 pin DIP provide further redundant power/ground, clock and address decode. If strictly required, a buffer card may be designed such that a bus is partitioned into segments and additional wait states are applied as signals traverse increasingly distance segments. It is also possible to use the 64 pin interface with 4MB SRAM modules and no additional logic or buffering.
However, in the trivial case, it wastes about 3/16 of the board area. It is rarely, if ever, worthwhile to implement the scheme partially or in full. After working through this exercise and several variants, I strongly advise against implementation of the 64 pin interface in any form. This is particularly true given that it is yet another incompatible bus connector. Therefore, if you must implement a parallel bus connector, use a design which is already in widespread use. Examples include S-100, Commodore 64 edge connector and
Planck Bus. However, the most affordable and most compact design omits any formal expansion interface. Should you require any expansion, follow BigDumbDinosaur's experience re-purposing an existing socket with no prior consideration for mechanical fixings.
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