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theperfectionist
 Post subject: W65C02S
PostPosted: Thu Mar 25, 2021 8:27 pm 
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Is the W65C02S bus asynchronous or synchronous ?
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theperfectionist
 Post subject: Re: W65C02S
PostPosted: Thu Mar 25, 2021 8:35 pm 
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I meant to ask if the W65C02S bus has a clock that coordinates read/write operations
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enso
 Post subject: Re: W65C02S
PostPosted: Thu Mar 25, 2021 8:37 pm 
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Sorry, I misread the question initially. But yes, there is definitely a clock, known as Phi2 used for all operations on the bus.

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enso
 Post subject: Re: W65C02S
PostPosted: Thu Mar 25, 2021 8:41 pm 
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Just to clarify, you do not need synchronous RAMs or anything like that. There is no clock to RAM or ROM chips. There is a single R/W pin on the CPU, and to generate separate READ and WRITE signals we generally qualify it with Phi2 to make sure that the address and data are stable.

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enso
 Post subject: Re: W65C02S
PostPosted: Thu Mar 25, 2021 8:42 pm 
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Take a look at Garth's primer at http://wilsonminesco.com/6502primer/.

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GARTHWILSON
 Post subject: Re: W65C02S
PostPosted: Thu Mar 25, 2021 8:43 pm 
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Quote:
I meant to ask if the W65C02S bus has a clock that coordinates read/write operations

Yes, it does. Data transfers between ICs are coordinated by the Φ2 clock signal. The symbol used is the Greek letter phi (not the diameter symbol, nor the crossed numeral zero, nor the empty-set character.) "Φ" is pronounced "fi," rhyming with "fly," or, less-preferred, "fee," rhyming with "flea;" but what it stands for here is "phase," and it's just as easy to say "phase two," like "gate one" for the 74xx138's G1 input. This clock is not for reading time of day but instead is a timing coordinator square-wave signal that typically runs at a constant frequency.

Unlike many other processors, a "cycle" on the 6502 consists of only the Φ2-low time followed by the Φ2-high time, in that order. The falling edge of Φ2 starts the next cycle. The 6502 does mostly internal operations in the first half of the cycle when Φ2 is low, and its bus accesses (reading or writing) when Φ2 is high. So for example at 1MHz, one cycle takes only one microsecond, unlike many other processors where they really mean an instruction cycle or a machine cycle, terms which are not used with the 6502. The 6502's bus cycle and a clock cycle are the same thing. Instructions take anywhere from two to seven cycles each, averaging around four, a little less if you're doing mostly zero-page operations, or a little more if you're doing lots of indirect and indexed operations.

(The above is from the address-decoding page of the 6502 primer. Edit: Thanks, enso, for the recommendation.)

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BigDumbDinosaur
 Post subject: Re: W65C02S
PostPosted: Thu Mar 25, 2021 11:06 pm 
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enso wrote:
Just to clarify, you do not need synchronous RAMs or anything like that. There is no clock to RAM or ROM chips. There is a single R/W pin on the CPU, and to generate separate READ and WRITE signals we generally qualify it with Phi2 to make sure that the address and data are stable.

Just for reference:

Attachment:
File comment: 6502/65C02/65C816 Read/Write Logic
read_write_qualify_alt.gif
read_write_qualify_alt.gif [ 46.98 KiB | Viewed 511 times ]

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