Hi all,

I'm trying to evaluate the suitability of various architectures for a hobby project I want to create. I've been having a close look at the 6502 and/or 65816, because it seems to me a very clean architecture.

I was wondering if anybody knew if there are any parts (or combinations I could invent) for wireless networking (whether that be GSM (SMS), something bluetooth-like, 802.11x, whatever) that would interface with the 6502 bus easily. I only need to send single packets to the device, basically with a set of instructions (would fit into the 160 character limit for SMS). No return data.

If not, does anybody have any suggestions for other architectures that can do this? I'm not a fan of the PIC architecture, but if it is the only choice I will. I'd rather use discrete components than microcontrollers.

Thanks so much for reading, and if you have any suggestions, thanks even more!

Jack

Have you looked to see if there are any SPI devices for what you want to do? I suspect there are, and Daryl here has a new 65SPI chip of his design available, to put directly on the 6502/816 bus. If it's not necessary to go as fast as possible, you can very easily bit-bang SPI through a 65c22 too.

I hear you there on the PICs. Terrible instruction set, terrible architecture. I'm working on another aircraft product right now with a PIC16F72.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks, that has opened up a whole series of options. I'm currently looking at one of these GSM modules. Unfortunately it doesn't list a price, which makes me think it's going to be very expensive. But it does have a TCP/IP stack built in, which would allow for world-wide control from basically any computer, in theory.

Another option is this 802.11b module which also has the TCP/IP stack built in... but again, expensive.

If I need something cheaper then I could go with one of these Ethernet modules. But I'd have to do TCP/IP myself.

I'll keep looking, and let you know what I decide. Thanks for the pointers so far!

Those have I²C too, and if that's fast enough, it's even easier than SPI (unless you need voltage level translation, which can be done in I²C but not as easily as in SPI).

I'm pretty sure the uIP TCP/IP stack is available already written for 6502. You might search this website and http://www.sics.se/~adam/uip/index.php/Main_Page .

Having had a look into the costs and so on, it appears the only thing I can afford to do is use ethernet, pretty much everything wireless (except infrared) is too expensive.

I'd like IPv6 support, so if uIP supports that I'll use it, otherwise I'll just write my own. Haha, it sounds like I want everything. Maybe I do...

I would have needed a power cable anyway though, if I went wireless. Or a massive battery pack for the stepper motors.

Oh well, off to do some more research on other parts of the project now, I'm still a bit of a n00b.

Thanks Garth.

I have another quick question if that is okay. What sizes of memory are available for the 65C816? I have read of 32Kx8 EEPROM and 512Kx8 SRAM, but can either of these go larger? I have been writing code for raw x86 systems, and 32KiB isn't a lot.

Hi Jack,

The 6502 can address 64k directly (16 bit address bus). The 65816 can address 16M directly (24 bit address bus).

With either, you can choose the amount of RAM and ROM. Unlike the x86, the 6502/65816 puts the I/O into the same address map as RAM and ROM, so you have to leave room for that as well.

As far as ROM, 32K can hold quite a bit. But your application will dictate the size. For instance, my SBC-2 contained a System Monitor (read/modify memory), XMODEM/Intel HEX file transfer support, disassembler, mini-assembler, and EhBASIC interpreter. It took about 18k to hold all of that.

Daryl

Single EPROMs go up to a couple of megabytes. Single SRAMs do too if 3V is ok (instead of 5V). There's usually no reason you can't use more than one though.

I've read elsewhere on this forum that it's better to place memory boundaries on the largest powers of two available. So my initial thoughts are something like follows:

000000h - 007FFFh (32KiB) 32Kx8 SRAM (placing some here due to direct page and stack having to be in first 64KiB).
008000h - 00FFFFh (32KiB) 32Kx8 EEPROM (same reason for reset vector)

The rest of the space between ROM and 1MiB in the address space will be filled with I/O devices (though obviously I won't be actually filling it). Any space from 1MiB up until 8MiB could be filled with more RAM or ROM, depending what I need.

800000h - FFFFFFh (8MiB) 4x 2Mx8 SRAM (in theory, in practise I'll add a first at 800000h and see if I need the additional chips)

My plan is to fit TCP/IP, DHCP and TFTP into the 32K EEPROM, then I can load the larger program through network.

So yeah, it does look as if I'll be using the 65C816 for the project.