Occasionally when working with old logic, you may find you need a non-overlapping complementary clock signal. Here's how to construct one without resorting to rare, out-of-production clock generator ICs:

1: Generate the positive clock and its complement in the manner of your choosing. They might be the complementary outputs of a flipflop, or simply generating the negative clock by passing the positive one through a NOT gate. These signals are synchronised in the long term, but are not guaranteed to be non-overlapping. We'll call them A and B.

2: Cross-couple a pair of NOR gates, as if you were building an SR flipflop. Connect A and B to the free inputs. The outputs are E and F, which are guaranteed to both be low for at least one gate delay between either being high. This guarantees that they are non-overlapping.

Hence E = ~(A | F), F = ~(B | E). This means F will have the polarity of A and E will have the polarity of B.

nice!

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

I think the 6502's on-chip clock generator does something very like this!
viewtopic.php?f=1&t=2412

One place where you might need this is when driving the 6512, which requires a Phi1 clock as an input rather than producing it as an output. This is the clocking scheme also used by the MC6800, for which Motorola provided a specialised, external clock generator IC. The basic 6502 was really designed around attaching a crystal or other resonator directly to the CPU.

The 6809E (and 6309E) requires a quadrature clock (E and Q) instead, with no requirement for complements or avoidance of overlap. The non-E suffixed versions generate E/Q clocks from a built-in oscillator. Generating a quadrature clock could be useful for DRAM based systems, even if the CPU doesn't actually require it. This is straightforward with a pair of cross-coupled JK flipflops, both clocked by the master oscillator at 4x output frequency. Given a master clock and its complement, you may only need 2x frequency although there may then be a slight phase offset from the ideal 90°. Both options are illustrated in the attached.

It is a neat trick. But I'd say that overlap should apply to 0 as well as 1. I.e. simply an inverter and non-inverter with equal propagation delay in parallel.

That may get you approximately simultaneous transitions of the two clock phases, which is sometimes what you want, but I'm talking here about devices which specifically require the guarantee that the two phases will never be high simultaneously. This is typically because they rely on dynamic logic, which would exhibit shoot-through in that case.

Yes. But I'd call that a 'non-overlapping high', not 'non-overlapping'. Just nitpicking, sorry.

It is specifically referring to the active periods of each clock phase being non-overlapping. If you need such signals to be active-low, simply substitute NANDs for the NORs in the first circuit above.

I argue purely about the terminology, not the practical aspects.

The nice thing about the cross-coupled NORs, if done right, is that the feedback signal can be from the actual clocks, so even if the two phases have different loads, the cross-coupling works out.

Approaches without that sort of feedback may need to be carefully balanced.

Generation of two non_overlapping complementary clock signals.

Starting to remember, that we had that sort of topic when dissecting the SID.

That diagram uses the DIN symbol for the NOR gates, which is extremely confusing when combined with the background grid which happens to align with the internal stripes.

Sorry that, for the first schematics in the SID thread the grid was turned on.

I'm adding a simplified (and maybe less confusing) monochrome picture: