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PostPosted: Tue Feb 09, 2021 8:46 am 
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GARTHWILSON wrote:
You're welcome. I wrote it in its original form about 20 years ago to answer questions and problems that kept coming up on the forum, but I didn't have my own website yet, so it sat collecting dust until 2012. Then I blew the dust off and made some upgrades, and posted it. I make frequent updates on it. There was something recently that made me think I should add another whole page. People have asked about more-advanced stuff though, which would not fit in the category of "primer," ie, the basics to get you going. There are of course many other major features on my site, including ones with many pages, the stacks treatise having the second-most pages, with 19 plus appendices. I plan to post a lot more material, but it all takes so much time. I did most of it at times that my job was slow.

As my younger contemporaries would say "Awesome bro!" And I've also printed out alot of your other features: "large math look-up tables", "65c02 assembly structure macros", "simple multitask", "6502 interrupts, "6502 stacks treatise" and "self-modifying code". Youth may prefer a digital screen, but I prefer hard-copies and enjoy writing notes on it. Given I and many others are from the era of the C64, this would be understood by most here on the forum.

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PostPosted: Tue Feb 09, 2021 8:50 am 
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BigDumbDinosaur wrote:
Firefox6502 wrote:
Why am I using 32k of ROM? LOL, I thought I'd need as much RAM and ROM as possible. Last I'd read (some 10 years ago), a simple "Hello World" application in .NET takes 23MB in size (incl. all the required libraries). I understand well that assembly is a different world, but I have the mindset of being a commercial high-level developer for close to three decades. Thinking about this further, I'm going to initially go with 8k ROM, and adjust as I go. Also thanks heaps for the tip, I will keep the ROM contiguous to make the programming more straight-forwards, especially for someone at my level.

One of the best features of 65C02 assembly language is its "economy of speech." Properly-written assembly 65C02 language programs tend to be succinct and fast-executing. This is in stark contrast to compiled languages, which tend to bloat up from attached libraries and limitations in trying to convert English-like statements into machine code. So you will be pleasantly amazed at how much 65C02 code you can stuff into 8KB of ROM.

BTW, here's a "Hello, world." program you can test after you get your machine going.


Code:
;print "Hello, world." on console
;
         ldy #0                ;string index
;
loop     lda hello,y           ;get from string
         beq done              ;null means end-of-string
;
         jsr putch             ;output char to console
         iny                   ;bump index &...
         bra loop              ;continue
;
done     brk                   ;function end (could be RTS instead)
;
;
;   text string...
;
hello    .byte "Hello, world!",$0d,$0a,$00

The above program is 14 bytes in length, not counting the actual text string. PUTCH would be defined as the entry pint for the function (subroutine) in your BIOS that writes a character to the console screen.

Thanks, this will be one of the code to execute on my SBC.

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PostPosted: Tue Feb 09, 2021 1:51 pm 
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Perhaps some additional food for thought... first on a memory map and how much RAM or ROM (EEPROM) you might want to consider.

1- Using a 22V10 for Glue logic gives you flexibility, which is good. Use this to provide chip selects for both RAM and EEPROM.
2- I would suggest using a newer 128KB Static RAM chip. You won't use it all, but by changing the GLUE logic, you can pick where RAM ends and EEPROM begins.
3- I would (also) suggest using a 32KB EEPROM chip. The same applies as above.... changing the GLUE logic allows you to use as much or as little as you need.
NOTE: 32KB EEPROMs are more readily available these days and can be had in 70ns access speeds.
4- PLD speed.... I'm using the slower low power ATF22V10CQZ in my latest C02 Pocket SBC, which is rated at 20ns. 8MHz clock speed is no issue. Faster parts use more current.

Carving out the hardware I/O space. We all have our own view on this.... there's no right or wrong answer either. There are 3 specific memory areas for the 65C02:
1- Page Zero, which is special and has it's set of addressing modes and unique instructions.
2- Page One ($01), which is the processor Stack (read up on this one).
3- The last page ($FF), which contains the address vectors for IRQ, Reset and NMI.

All of the above are not alterable, so you need to fit everything within those constraints. I did my first SBC in the latter 80's and adopted a memory map that I still use. In my simple view, RAM grows from the bottom up and ROM from the top down. I decided to put all I/O on Page $FE. While this can easily result in non-contiguous ROM usage, what does it matter? If I decide to add a bootable device, like an IDE controller, I would be able to fit the boot code into less than 256 bytes and have mostly RAM with the exception of the last 512-bytes (for example). In my view, this memory map gives me the largest possible contiguous "memory". Note that I consider this to be the memory address range starting from $0200 and going as high as $FDFF, which is 63KB. Using a single Glue logic chip allows you to pick the dividing line between RAM and ROM.

Second, some classic code on the 65C02. BDD already showed a classic character out routine. However, it only allows for 255 bytes of a maximum string size, as it uses the Y index register. It is very efficient in both code size and execution time. If you need to output multiple strings in your code, then you might want to look at something with a bit more flexibility. I use an index table in my monitor code, which allows a single value (in the A reg) to define a message. The output routine uses the single index value as a look-up index to a table, then grabs the actual memory address for the respective message and loads that value to a page zero area. It's a bit more code of course, but handles larger messages and the one routine can be used for any and all messages.

Code:
;PROMPT routine: Send indexed text string to terminal. Index is contained in A reg.
; String buffer address is stored in variable PROMPTL/PROMPTH.
PROMPT          ASL     A               ;Multiply by two for msg table index
                TAX                     ;Xfer to X reg - index
                LDA     MSG_TABLE,X     ;Get low byte address
                LDY     MSG_TABLE+1,X   ;Get high byte address
;
;PROMPTR routine: takes message address in Y/A and prints via PROMPT2 routine
PROMPTR         STA     PROMPTL         ;Store low byte
                STY     PROMPTH         ;Store high byte
;
;PROMPT2 routine: prints message at address (PROMPTL) till null character found
PROMPT2         LDA     (PROMPTL)       ;Get string data
                BEQ     EXIT            ;If null character, exit (borrowed RTS)
                JSR     B_CHROUT        ;Send character to terminal
                INC     PROMPTL         ;Increment low byte index
                BNE     PROMPT2         ;Loop back for next character
                INC     PROMPTH         ;Increment high byte index
                BRA     PROMPT2         ;Loop back and continue printing
EXIT            RTS                     ;Exit
;


Needless to say, there's always multiple ways to get something working with the 65C02 assembly language.... and as I like to say, you can't (always) argue with success. You can code for minimum size or you can code for minimum execution speed... and sometimes reach a happy median.

Getting some good references would also be a plus:
1- Programming the 65816 by David Eyes and Ron Lichty (includes the 6502 and 65C02)
2- 6502 Assembly Language Subroutines by Lance Leventhal and Winthrop Saville

Of course, best of luck in getting your first SBC up and running. Do look through other people's code to get ideas and examples on how to get some basic building blocks for the 65C02. They will come in handy as you move forward.

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https://github.com/floobydust


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PostPosted: Wed Feb 10, 2021 8:58 am 
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floobydust wrote:
Perhaps some additional food for thought... first on a memory map and how much RAM or ROM (EEPROM) you might want to consider.

1- Using a 22V10 for Glue logic gives you flexibility, which is good. Use this to provide chip selects for both RAM and EEPROM.
2- I would suggest using a newer 128KB Static RAM chip. You won't use it all, but by changing the GLUE logic, you can pick where RAM ends and EEPROM begins.
3- I would (also) suggest using a 32KB EEPROM chip. The same applies as above.... changing the GLUE logic allows you to use as much or as little as you need.
NOTE: 32KB EEPROMs are more readily available these days and can be had in 70ns access speeds.
4- PLD speed.... I'm using the slower low power ATF22V10CQZ in my latest C02 Pocket SBC, which is rated at 20ns. 8MHz clock speed is no issue. Faster parts use more current.

Carving out the hardware I/O space. We all have our own view on this.... there's no right or wrong answer either. There are 3 specific memory areas for the 65C02:
1- Page Zero, which is special and has it's set of addressing modes and unique instructions.
2- Page One ($01), which is the processor Stack (read up on this one).
3- The last page ($FF), which contains the address vectors for IRQ, Reset and NMI.

All of the above are not alterable, so you need to fit everything within those constraints. I did my first SBC in the latter 80's and adopted a memory map that I still use. In my simple view, RAM grows from the bottom up and ROM from the top down. I decided to put all I/O on Page $FE. While this can easily result in non-contiguous ROM usage, what does it matter? If I decide to add a bootable device, like an IDE controller, I would be able to fit the boot code into less than 256 bytes and have mostly RAM with the exception of the last 512-bytes (for example). In my view, this memory map gives me the largest possible contiguous "memory". Note that I consider this to be the memory address range starting from $0200 and going as high as $FDFF, which is 63KB. Using a single Glue logic chip allows you to pick the dividing line between RAM and ROM.

Thanks! Great idea regarding the larger RAM size. I would definitely benefit from this esp since my ROM code would be very small.

Question 1: Why get a 128KB RAM chip? Why not a 64KB RAM chip, as the most you can address for RAM would be is 63.9KB (and page $FF for the ROM chip).

Question 2: On this topic, why not get a 64KB RAM chip and 64KB EEPROM chip, this way, if I wanted to go the other way and need heaps of ROM and little RAM, I could program the PLD accordingly? I'm sure this scenario would be rare, but this design would give the option if ever needed.

BTW I really love your memory map. The ROM page and the I/O page fit so well next to each other - very neat!

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PostPosted: Wed Feb 10, 2021 9:48 am 
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32kB and 128kB RAM\EEPROM\Flash memory chips are available.
But 64kB memory chips usually are not.

On the bright side, using a 128kB EEPROM\Flash chip gives you the option for booting from two different 64kB ROM blocks\images,
selected by using a jumper to GND and a pullup resistor to VCC connected to the A16 address input of the chip.

For instance: one 64kB block contains your code, and the other 64kB block contains some tools for testing the hardware of your SBC.


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PostPosted: Wed Feb 10, 2021 7:03 pm 
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The other factor for the 128k devices for rom is cost. Buying new, a 32k eeprom (28C256) will likely cost you at least 5x a 128k flash (39SF010). Having just had a look at Mouser there's very little differecne between their 32k and 128k static rams. Getting the larger size adds flexibility for little if any penalty.


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PostPosted: Sat Apr 24, 2021 11:05 pm 
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Martin A wrote:
The other factor for the 128k devices for rom is cost. Buying new, a 32k eeprom (28C256) will likely cost you at least 5x a 128k flash (39SF010). Having just had a look at Mouser there's very little differecne between their 32k and 128k static rams. Getting the larger size adds flexibility for little if any penalty.

Hi guys, work and life had called me away from the 6502 lifestyle, but back in again... woot!

Two questions...

ROM
I noticed most people use an EEPROM chip for their ROM, but flash memory was mentioned in the post above, so are there any disadvantages to using flash memory (over EEPROM) for ROM?
And does programming flash memory still involve using a chip programmer?

As mentioned above, memory capacity and costs differ greatly between the technologies (prices from au.mouser):
SST39SF010A-70-4C-PHE (128K) is $1.84
https://au.mouser.com/ProductDetail/Microchip-Technology/SST39SF010A-70-4C-PHE?qs=%2Fha2pyFadugYEi%252BidWLSZJVjq3ZtY5NTxqr%252BYnW9Usc%3D

AT28C256-15PU (32K) is $13.85
https://au.mouser.com/ProductDetail/Microchip-Technology-Atmel/AT28C256-15PU?qs=%2Fha2pyFaduhILzlGikUCkpQbxe88tIlxTAG%252B92t72jM%3D
Both chips speeds are 70ns.

I'm assuming EEPROM is an older technology which was more accessible and commonly used back when people were building their SBCs. Now that Flash technology is more common and cheaper, Flash memory is the way to go (just a guess).



RAM
This may be a dumb question... I believe I've found the equivalent SRAM 128K chip to use (instead of a 32K chip), could someone please confirm this selected 128K SRAM chip is compatible for use with a 65C02 SBC.

AS6C1008-55PIN (128K) is $5.12
https://au.mouser.com/ProductDetail/Alliance-Memory/AS6C1008-55PIN?qs=FP1Nkeq3mZ9b%2FgtA0ttBwQ%3D%3D

Where I would have been using a 32K ram chip such as this below:
AS6C62256A-70PCN (32K) is $6.35
https://au.mouser.com/ProductDetail/Alliance-Memory/AS6C62256A-70PCN?qs=%2Fha2pyFadujm1%252BmXP6%2FY0Pw%2FxLDHLmf64oJZ86zfGThh12Y6tFsrNw%3D%3D

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PostPosted: Sun Apr 25, 2021 7:09 am 
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Firefox6502 wrote:
ROM
I noticed most people use an EEPROM chip for their ROM, but flash memory was mentioned in the post above, so are there any disadvantages to using flash memory (over EEPROM) for ROM?
And does programming flash memory still involve using a chip programmer?

The 32-pin package does require a bit more space on the circuit board. Commercial programmers should work. I use a custom Arduino shield to program the SST39 series 128K, 256K, and 512K flash chips as well as the 28-pin AT28C256 EEPROMs. The design is similar to one of the many Arduino EEPROM programmers but with a 32-pin ZIF socket and a few extra address lines.

Image
Image

Quote:
I'm assuming EEPROM is an older technology which was more accessible and commonly used back when people were building their SBCs. Now that Flash technology is more common and cheaper, Flash memory is the way to go (just a guess).

I agree.

Quote:
RAM
This may be a dumb question... I believe I've found the equivalent SRAM 128K chip to use (instead of a 32K chip), could someone please confirm this selected 128K SRAM chip is compatible for use with a 65C02 SBC.

AS6C1008-55PIN (128K) is $5.12
https://au.mouser.com/ProductDetail/Alliance-Memory/AS6C1008-55PIN?qs=FP1Nkeq3mZ9b%2FgtA0ttBwQ%3D%3D

Where I would have been using a 32K ram chip such as this below:
AS6C62256A-70PCN (32K) is $6.35
https://au.mouser.com/ProductDetail/Alliance-Memory/AS6C62256A-70PCN?qs=%2Fha2pyFadujm1%252BmXP6%2FY0Pw%2FxLDHLmf64oJZ86zfGThh12Y6tFsrNw%3D%3D

Yes, that 128K RAM chip should work fine. Also, 'skinny' 64K RAM chips like W24512AK, UM61512AK, and IS61C512 are available from Chinese sources at quite reasonable prices but at the expense of long shipping times.

Cheerful regards, Mike, K8LH


Attachments:
6502 Socket.jpg
6502 Socket.jpg [ 290.29 KiB | Viewed 677 times ]
6502 64K Socket.png
6502 64K Socket.png [ 102.55 KiB | Viewed 677 times ]


Last edited by Michael on Sun Apr 25, 2021 7:51 am, edited 1 time in total.
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PostPosted: Sun Apr 25, 2021 7:25 am 
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I wonder if anyone has worked out the GAL logic necessary to boot from ROM in order to copy a monitor and OS image into RAM and then switch out the ROM for a 64K RAM system?

BTW/FYI... I'm building a programmer for the Atmel 16V8B and 22V10CQZ GAL devices based on this Afterburner programmer project.

Cheerful regards, Mike, K8LH


Attachments:
GAL Afterburner 3.png
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GAL Afterburner 2.png
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PostPosted: Mon Apr 26, 2021 12:29 am 
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Thank you very much Michael. I'm continuing to design and build.

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