Hello. I started a project making a 6502 from scratch before I discovered 6502.org. I am looking at making an asynchronous implementation targeted for passively-powered RFID, and I'm in the preliminary logic stage.

I've noticed that there are undocumented opcodes, which are actually just incomplete logic trees. I have two questions:
1) Are any of these undocumented OP codes used in practice?
2) I currently have all undefined sequences become NOP instructions. What is the proper way to handle these if you cannot replicate the original functionality.

Asynchronous logic uses dual-rail encoded signals and completion trees to clock the system, and the undefined instructions cause a problem in the completion logic.

Any suggestions would be appreciated.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thank you! That's an excellent resource. I'll dig in and see.
I don't use a PLA structure due to the completion trees, so i might not end up being illegal op code compatible, but I'll see what I can do.

Cheers.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I'll take a look at that. I was looking for a non-IP encumbered core with a low transistor count. 6502 also had a huge software and knowledge base, which made it interesting. I will look at the 65c02 as well.
I can use a PLA as long as I handle all of the corner cases. I expect the final device will run between 1Hz and 1GHz, but I'm still trying to feel my way through the application space and the silicon space. I appreciate the links. I poorly approached this by reading an old book instead of asking google. :/
Again, I appreciate the guidance.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Not all of the invalid NMOS 6502 opcodes are stable.
Some of the invalid opcodes could give you different results on different chips.

Old software isn't supposed to make much use of them.
When writing new software, best practice is to avoid using them.

Please take a look at the C74 project,
that's a 20MHz TTL CPU which is mostly timing compatible and cycle compatible to NMOS 6502 and 65C02,
although the internal architecture is different from these chips.

Recommended reading:
6502 undocumented opcodes
6502 unstable undocumented opcodes
6502 dead cycles
C74 block diagram

In the C74 project, we started to call the invalid opcodes UFOs: instructions UnFOrseen by the designers.

For an asynchronous 6502 VHDL implementation, please take a look at the PSALM project from 2001,
but be warned that all of the text seems to be in German language.

Hope, this helps.

Welcome, bpdegnan!

In my view you should feel free: the easiest route is to ignore the undocumented opcodes, allow your machine to do whatever it happens to do. That's what the original NMOS 6502 designers did. If you like NOPs, go ahead, but it might take more logic. If you like the 'C02, go with that, it's certainly more logic, but perhaps not too much.

Some software did use undocumented opcodes: some games, many demos, some software protection routines. If that software falls inside your area of interest, so be it. As ttlworks says, the undocumented behaviour is not all precisely specifiable. For me, a great reason to ignore it. For some, a challenge.

When deciding what to implement, you might also make a choice about BCD arithmetic: ignoring it will reduce the logic, but you need to know that your software won't use it. Being faithful to the NMOS 6502 behaviour for sensible BCD inputs is the next level, and then beyond that you can try to be faithful to undocumented behaviour or to choose 'C02 behaviour.

Good luck with the project!

Right, BigEd: BCD arithmetic is going to be another can of worms.

65C02 sets the flags correctly for decimal mode ADC and SBC, but NMOS 6502 does not (it sets the flags according to the result before the decimal correction).

There is a little difference between NMOS6502 and 65C02 in the decimal mode SBC results when subtracting non_decimal numbers.

Do you plan on running existing code or writing all new code for your project? If it's the latter, you could consider reassigning the unused op codes to custom functionality instead of making them NOPs. That way you can take advantage of existing assemblers and compilers and still have a route to make your processor more efficient and easier to program. Something like the 65CE02, for example, might be a good starting point.
6502 is a good choice I think. Have you looked at the 8051 also? No clue about the IP but it seems to get pressed into service for all kinds of things where a bare minimum 8 bit architecture is needed.

There's an index thread of previous threads about extensions - it's often thought about:

Index of threads for improved 6502 and derived architectures

I will be writing new code. To that end, I might also drop the zero-page addressing as everything will be on die.
Mainly, it's a low-transistor count, proven architecture. I've decided against the 8051 just because of complexity.
As I said above, I'm targeting an asynchronous implementation for battery-free devices, which is why I needed minimal transistor count. It cost me 2x the transistors, plus a completion tree circuits to go asynchronous. The 6502 architecture does quite a bit for what it is, and I really didn't find something that I could definitely describe as better. There's also C compilers but the assembler is just so easy.

If the goal is minimal transistor count, then you could consider drastic measures such as eliminating one of the index registers. (Somewhere on this forum there's mention of something along those lines -- a sub-6502 intended for cost-sensitive applications -- toys, IIRC.)

Hmm, but the memory requirements for your code will increase to some degree... although perhaps not by much in simple applications.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

One index register, like in the 6800 ?
This would make moving blocks of data in memory pretty inefficient.


IMHO a lot of the complexity in the 6502 PLA comes from the fact that data is 8 Bit and address is 16 Bit.

If data and address both would be 16 Bit, I think this would simplify the PLA a lot,
but then the CPU won't be 6502 compatible anymore.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?