6502.org Forum  Projects  Code  Documents  Tools  Forum
It is currently Thu Nov 14, 2024 5:25 pm

All times are UTC




Post new topic Reply to topic  [ 19 posts ]  Go to page Previous  1, 2
Author Message
PostPosted: Fri Jan 29, 2021 6:43 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8484
Location: Midwestern USA
Like Garth, I have a hard time correlating a schematic that is boxes with net symbols to the circuit's intended function, but I think I can offer one sage bit of "wisdom."

I presume you know who "Boss" Kettering was. My mentor back in my railroading days once referred to "Boss" Kettering as the Yogi Berra of the automotive industry due to Kettering's common-sense observations about automobile design and manufacturing. Foremost among those witticisms was "Parts left out don't cost anything and never break." (Note that Kettering's exact words have long been a topic of debate, but what he meant is crystal-clear.) In other words, design for simplicity and your contraption will be cheaper to make and easier to repair.

"Boss" Kettering's aphorism, if applied to computer design, could be paraphrased as "Gates left out don't clutter the design and don't cost propagation time." My impression of your circuit is the glue logic is torturous and needs to be given some more thought. A worthwhile goal, one that I routinely seek in my designs, is to have no more than two cascaded gate delays between the address bus and any one chip select. It's not easy, but can be done.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Top
 Profile  
Reply with quote  
PostPosted: Fri Jan 29, 2021 10:03 am 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10977
Location: England
I haven't looked at the schematic, but BDD's comments remind me of something. If you have complex logic, where various inputs diverge and reconverge to produce a result, it's possible that the result will be glitchy - in fact it's relatively likely. Modern design advice is, as much as practical, to use synchronous design style with a single clock, and in the ideal case glitches (or non-monotonic outputs) are then not a problem, provided everything settles by the time of the next clock edge.

However, if you do have a non-monotonic output, or a glitch, which happens at some time, then the circuit may work if the next clock edge comes either after the glitch has settled, or before it arises.

That's a possible explanation for why a circuit might work at a high speed but some lower speed. It's actually being clocked too fast for the various propagation delays, but happens to come out right in this particular experiment.

It might or might not be the root cause here!


Top
 Profile  
Reply with quote  
PostPosted: Fri Jan 29, 2021 12:32 pm 
Offline

Joined: Thu Oct 29, 2015 8:07 am
Posts: 6
If I'm reading the schematic correctly you're qualifying CS_RAM with PHI2, while R/W is connected straight to the SRAM's WE pin. You should instead be qualifying WE with PHI2, and CS_RAM should be decoded with as few gates as possible. You have a lot of cascaded logic for the chip selects.


Top
 Profile  
Reply with quote  
PostPosted: Fri Jan 29, 2021 3:18 pm 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8484
Location: Midwestern USA
BigEd wrote:
I haven't looked at the schematic, but BDD's comments remind me of something. If you have complex logic, where various inputs diverge and reconverge to produce a result, it's possible that the result will be glitchy - in fact it's relatively likely.

Going along with your theory (which I think is the likely scenario in this case) is the fact that propagation delays are somewhat random in nature, due to the usual device tolerances. Furthermore, temperature and/or voltage variations can vary the aggregate prop delay over the short term and further randomize things to where glitches can come and go with no obvious explanation.

MagerValp wrote:
If I'm reading the schematic correctly you're qualifying CS_RAM with PHI2, while R/W is connected straight to the SRAM's WE pin. You should instead be qualifying WE with PHI2, and CS_RAM should be decoded with as few gates as possible.

Those are points I earlier mentioned. The main concern with not qualifying /WE is the risk of corrupting data in an RAM cell that is incidentally selected as the address bus settles during Ø2 low. Hence the risk of corruption if /WE is asserted during Ø2 low.

A slightly more complicated situation exists with the 65C816, which drives the data bus during Ø2 low to emit the A16-A23 component of the effective address. Hence a device's /OE must not be asserted until Ø2 high to avoid data bus contention. Lacking that, a bus transceiver would have to be used for isolation.

Quote:
You have a lot of cascaded logic for the chip selects.

That he does. Aside from the potential glitching issue mentioned by Ed, there is the question of whether the logic in fact does what is expected. That can be hard to determine when gate after gate is used to generate an output.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 19 posts ]  Go to page Previous  1, 2

All times are UTC


Who is online

Users browsing this forum: No registered users and 12 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: