To start a new thread ... the Micro-PET has a very simple SPI interface, and can boot from it.

- the Micro-PET has a very simple SPI interface included (but that only runs in mode 0 and fixed clock), it has a nice feature that reading the data register triggers another byte transfer, so while you store the byte just read, the next byte is already read from the SPI. Only if you read the "peek" register you get the data without triggering another transfer. See here hhttps://github.com/fachat/MicroPET/blo ... LD/SPI.vhd and associated documentation https://github.com/fachat/MicroPET/blob ... PLD/SPI.md

- the Micro-PET boots from SPI, with a very simple schematics: on "ipl='1'" the IPL code shifts out the Flash read command and address zero, then counts 256x8 bits to be shifted in. During shift-in, the address lines are set to high (A8-18), or fed from the IPL counter (A0-7), and set to write, while the shift register output is directly fed to the databus. So the top 256 bytes are loaded into the top of RAM - from where the CPU then boots! See basically the last 60 lines of https://github.com/fachat/MicroPET/blob ... LD/Top.vhd and some 'if's triggering on the 'ipl' signal.

So, if I have a CPLD on a board, I'll never use a parallel ROM ever again

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Hi!



This is almost the same as my SPI interface https://github.com/dmsc/my6502/blob/master/rtl/spi.v
The register definitions are at https://github.com/dmsc/my6502/blob/mas ... es.inc#L45 , and the code to read one sector is at https://github.com/dmsc/my6502/blob/mas ... m.asm#L190

My registers are only two:



The difference is that I only initiate a SPI read/write on a WRITE to the data hold register, I try to avoid performing operations on register reads, as the 6502 can do extra memory reads to unrelated locations, and also this allows to write and read in the same transaction (some devices need this).

The other difference is that I automatically handle CS on the first write to the data register, and the SPI is ended on a write to the control register, with the MISO and MOSI pins tri-stated so that I can write the flash while the board is running.



So, the CPLD reads the first 256 bytes on boot - this is actually a very good idea. My design (as is FPGA based) simply encodes the boot ROM (from $FF00 to $FFFF) in the FPGA, and here the boot code loads the first 256 bytes of flash to address $200, searchs for a proper "boot" signature and jumps. If no signature is found, a simple serial monitor allows to interaction via the serial port.

Have Fun!

Ah, the joys of completely replacing clunky parallel ROMs with elegant serial ones. I'll join in ... Two of my own products do something very similar. A tiny bit of hardwired bootstrap code inside a CPLD (which is always surprisingly cheap in terms of cells), just enough to load a single page of secondary bootstrap from serial ROM, quite enough to load everything else needed.

Good times.

All right, I'll join the fun. Here are several fairly recent (last 3 years) bootstrap methods:

Tiny68K uses a state machine in CPLD (EPM7128S, same as ATF1508AS) to load 32K serial EPROM (AT24C256) into DRAM starting from location 0x0 then release 68000 to run.

Z280RC uses a state machine in CPLD (EPM7128S) to initialize CF disk to read master boot record, then map (temporarily) CF's 16-bit wide data to memory from 0x0-0x1FF. Z280 reads and executes the 16-bit instructions coming out of 256 x 16-bit wide FIFO. That was an interesting program to write.

G8PP has a serial port and DMA logic in CPLD (EPM7128S) and jumper selectable serial bootstrap or RAM bootstrap modes. In serial bootstrap mode, DMA controller is the bus master at power up waiting for 256 bytes of binary serial data. If the processor is Z80, 8085, or 68008, serial data is DMA to low memory; for 6809 and 6502 it is DMA to high memory. When the 256th serial data is received, processor becomes the bus master and boot normally. The RAM is battery backed so in the RAM bootstrap mode, the target processor is the bus master and boot normally.

ZRCC has a serial port and small ROM in CPLD (EPM7064S, same as ATF1504AS). At power up Z80 executes the small CPLD ROM polling serial port or CF disk continuously. If a character is received from the serial port, it is in serial bootstrap mode waiting for 256 more bytes to be loaded into RAM and execute. If CF disk ready is detected, then it is CF boot mode where bootstrap program in master boot record is read into RAM and execute.

ZZRCC has a tiny CPLD (EPM7032S, same as ATF1502AS). A jumper selection decides whether Z280 boots with its native serial bootstrap mode or boots with the small ROM in CPLD.

CRC65 is the current project. It is like ZRCC with a serial port and small ROM in CPLD (EPM7064S) except the processor is 6502.

Bill