I have built a zero-glue Z80 a year and and half ago. Now I'm into 6502, I'm thinking whether it is possible to have zero-glue 6502 SBC as well. I think it is do-able, but maybe others have done it already. I would like to see examples of minimalistic 6502 designs.

My idea with zero-glue SBC was around the notion of shadow-write. i.e., RAM, ROM, I/O are all enabled and writable but only one device's output is enabled for read. ROM's output is enabled at power up, ROM owns the entire memory space initially; it writes to RAM so RAM/ROM have the same value. When transition from ROM to RAM, both devices' outputs are enabled for few instructions, but because they have the same values, there are no contention. The I/O device is also enabled and write only. The discrete outputs of the I/O device is used to switch on RAM, switch off ROM, and switch itself on.

In this scheme, RAM is the standard 128Kx8 with two chip selects; the active low chip select is grounded and the active high chip select is connected to CLK so RAM is active only when clock is high. RAM's write enable is connected to 6502 RWB, RAM's output enable is connected to discrete out of I/O.

ROM's chip select is grounded (asserted) and ROM's output enable is tied to another discrete output of the I/O

I/O is 16C550. It has active high read and write enables and active low read and write enable so it can be wired to be write-only initially but become read-write with one of its own discrete output. 16C550 also has multiple chip selects that can be wired to high address lines, so it does not take up too much memory space. <- I see a problem here: RAM needs to be turn off when I/O is accessed.

Please excuse me if this is all being done already, I'm new here.
Bill

Nice story for ROM and RAM. And writing a peripheral is fine, as you say. But how to get input? Perhaps the interrupt inputs can help?

Or, something with diodes or resistors, write 00 or FF to the RAM, and arrange that the peripheral can overdrive the RAM content when it's read.

I looked into 16C550 in greater details. The address strobe (ADS) signal has setup & hold requirements such that it needs to assert last and negate first. So if I want to use 16C550, I will need some kinda inverting gate with clock as part of the inputs. Oh well, I'll go think about other approaches.
Bill

I've yet to see a viable zero-logic 6502 design, but won't say it's impossible. To me the question would be "What's the point?"

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Good grief BDD, how many times? If you don't like a project, leave it to people who are interested.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Sometimes the pieces fit perfectly in a box but most times they don't, that's just the nature of the problem. I'll just let the problem simmer; maybe something neat will come out.
Bill

The reason this can work much more easily for Intel-bus systems is that you have extra address space already decoded for I/O by the CPU (the in/out ports). On a system without this (i.e., using a single 64K address space with memory-mapped I/O) the only "single-line decodes" you have are for upper versus lower 32K blocks of memory space (A15), and halves of any of those blocks.

So it seems to me that you're going to be looking at a situation where you have no more than 32K and perhaps much less RAM available (not a problem in my book) and you're relying pretty heavily on devices with multiple chip select inputs that have the correct polarities.

The RAM side is pretty easy as far as select goes: you can make /A15 ("not A15" = A15 low) the enable for a 32K RAM chip. But an issue here is that the RAM write signal typically needs to be qualified by Φ2, and that seems hard without logic.

The MC6821 PIAs have three select lines with both positive and negative logic (CS0, CS1 and /CS2), giving you a fair amount of flexibility about where you could fit one or two of these in your system, giving you parallel I/O and bit-banged serial if you like.

The ROM seems to be the big issue, since you have to produce the reset vector in the top two bytes of the address space. If using an address line signal, this implies an inverter being necessary to enable any JEDEC ROM. So it seems that the enable must come from somewhere else. Even if it's something we need to change programatically, we can still use your trick from the other system where ROM is enabled at startup, we copy our system code from ROM to RAM, and then disable ROM for further operation. (In this case, the ROM disable might reveal the I/O devices.)

Unfortunately, the PIA pins are all inputs on reset, so it doesn't seem we've got any help from that direction. Perhaps we can choose another I/O chip that will give us what we need.

This is a really interesting exercise, but due to the lack of a separate, pre-decoded I/O address space in Motorola-style systems, I think it's not going to produce a board that's really a "standard-style" SBC the way the Intel-style system did. If that's the real aim, going with an additional NAND gate and a 32K RAM/16K IO/16K ROM system seems to be the right direction.

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Curt J. Sampson - github.com/0cjs

Curt,
Good analysis.

128KB RAM has active high chip select as well as active low chip select. So the active high chip select can connect to clock and active low chip select can connect to I/O chip select that's active high. That way when I/O is selected, RAM is deselected. RAM's output enable is controlled by I/O's discrete output. Tri-state at reset is OK, because it can be pull-up.

ROM does not need to be qualified, its address and data can bounce all over the place as long as the right values are present right at the falling edge of 6502 clock.

I/O is the key; it needs programmable discrete outputs; it needs multiple chip selects so it doesn't take too much memory space; and it needs to leave top of memory free for interrupt vectors. You are right that having separate I/O and memory spaces in Z80 was the key for the zero-glue Z80 SBC.
Bill

Ah, Curt has something there: there are 16 address line outputs. We may have to be much more modest in the size of machine we can make, but surely there's a way to use the top two, or three, or four address lines to help with chip selects?

And maybe it won't always be chip select inputs as such - maybe other inputs, such as OE, could be used for selection.

Maybe have a look at this for some inspiration/ideas...

http://sunrise-ev.com/6502.htm

It does have a decoder - half a 74'139 which is used to qualify R/W, RAM and ROM selects and a single output enable - for 2 x 8-bit latches which use address lines in interesting ways. It's single-bit input is via the IRQ pin.

CPU, RAM, ROM, IO is do-able with one glue chip (I do it on my Ruby 6502 board with a cheaty GAL, but no glue? Tricky.

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

I don't think "no glue" is realistic for a 6502. A 6510, perhaps, as the processor port constitutes enough I/O to interface to, say, an I2C bus.

Another thought... But it depends on how much RAM you need... is 128 bytes enough? If so, then what about the 6532 RIOT. ...

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

That's a great little design that I quite like, but it feels like a dead end, in that as soon as you're willing to add a single logic chip, you've got the inverter (or similar) that you need and the whole puzzle becomes almost trivial to solve.


Yes, that's what I was getting at when I said, "...and halves of any of those blocks." (And yup, the OE also serves as a second "select" for the ROM.)

One opening is perhaps in my erroneous comment that "the reset vector [is] in the top two bytes of the address space"; it's actually in $FFFC/$FFFD, of course. (I have 6800 on the brain, as usual.) That actually does give as A1 low when reading the reset vector, though things then get difficult trying to handle an address space where alternate pairs of bytes are disabled/enabled at startup.

But now that I think about it, the solution to the select issue is probably easy enough: put one of the ROM selects on a PIA line with a pull-down, so that it's selected at startup when the line is an input, but after the system's started and you've copied your OS to RAM you can use that PIA pin to bring that line high. (I hope. It's going to have to be a very weak pull-up, I think, because the 6821 pins have very little drive.)

That still doesn't offer a solution to the RAM write qualification problem, though.

I did just have a look at the MC6850 ACIA data sheet to see if that might help, and it does indeed have its /RTS output (pin 5) low on reset, but unfortunately, unlike the 6821, the chip is not reset with an external signal but instead by writing a register (%xxxxxx11 to the control register), so there's no reliable help there.

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Curt J. Sampson - github.com/0cjs

Back when 6502’s were current, it was quite possible to build a respectable glueless system by using 6530’s. These were mask programmed (for the ROM), but they also included address decode logic that could be configured at the same time. Somewhere, in a data sheet I think, but I can’t locate it now, there is an example schematic showing 8 6530’s connected to a 6502 with zero glue logic. They are programmed to give 8k ROM, 128 I/O lines, and 512 bytes of RAM. That’s not possible today because we can’t order mask programmed parts.

Further down the line there are microcontrollers which could be used glueless. The R6501Q (or R6511Q) has all the I/O you would need, including a serial port, and could quite simply be connected to ROM and RAM. The latest Rockwell microcontrollers, which are a bit harder to find, have 4 address select lines and a banking system that provided full decoding for up to 4 devices in a 512k address range.

With a standard 6502 it may be possible to select the right chips to achieve a workable end result. As already mentioned a 32k RAM could be used with PHI2 and A15 connected to the select lines. The ROM is more difficult as a standard chip like a 2764 has only active low select lines, and we need the ROM to be at the top of the address range. I can’t think of a way around this, unless there is another chip that does have an active high select line. At this point it seems rather pointless to continue as with just one 74 logic chip the whole thing becomes possible and a lot more practical.