Although you may find schematics of people including the PHI2 clock in the /CS circuitry for a SID chip, Commodore does not appear to do this in their Commodore 64 schematics, for example in this one.

Is the system slow enough for the SID chip?

Mark

This is the part of the data sheet that I consulted when coming up with the timing.

The SID works at 1mhz so yes it is.

Yeah you're right, Commodore has it direct. The commodore works at 1.023 MHz and the Replica 1 works at exactly 1 MHZ. I wonder if that small difference could cause the timing issue. It just seems weird to me that the only other SID to Apple schematic I found did the same thing as me.

None of this contradicts what's implied by their Typical Application schematic.

Understood! But misunderstandings happen. And a surprising amount of stuff that's misconceived in various ways nevertheless manages to (more or less) work -- it's quite astonishing.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Interesting. I'll run some more configurations and see if I can get something closer to what the illustration in the data sheet shows. It's possible that jeff was right and it's entirely delay related.

If you need further assistance, can you PLEASE show us some photos of your setup?!!

(On this forum you're permitted to attach images with your posts.)

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

PHI2 should be connected to pin 6 on the SID, presumably because it has internal circuitry to qualify /CS and R/W.

I can’t see that making any difference.

If the Replica 1 uses modern CMOS chips, they often have much quicker translations between logic levels, so it may be worthwhile checking that the timings are okay.

Mark

I've used an original MOS6526 in my SBC with modern WDC parts, a 65c02. /CS is not qualified by PHI2, only by the address bus, and it works.

As far as I know, no 65xx device needs it's /CS qualified by PHI2 as it handles it internally.

I just saw... You have R/W tied to ground. Why? It should be connected to the CPU R/W directly. This way, you maybe writing invalid data to the sid, and by qualifying it with PHI2 may be solving this issue.

Could you give it a try this way?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Interestingly, when I had RW tied to the line on the computer nothing would happen. When I first connected it I did it like the suggested configuration shown in the data sheet, but there was no response. I must have tried wiring it that way at least 10 times and I still had no luck.

The expansion bus of the Apple 1 (and Replica 1) is a pretty straightforward exposure of the 6502 bus, plus some minor high-order address decoding lines. It even includes the Phi0 clock for reasons I don't fully understand.

The SID expects to be connected pretty much directly to a 6502 bus. The datasheet explicitly says that /CS could be generated through a mere address line, though it would be far more common to run it through some decode logic first; either way, the timing diagram shows no relationship with the active Phi2 edge, and only says that the access time is to be calculated from the last active edge among Phi2, /CS, and addressing signals. The C64 decodes a rather generous portion of address space for the SID. It's important to remember that /CS is active-low; this is satisfied by the $A000, $B000, etc decode lines provided at the expansion ports.

The fact that this configuration doesn't work for you suggests strongly that you've missed some other detail - such as power supply bypass capacitors, which are roughly ten times as necessary on the wrong side of an expansion port than directly on the motherboard, and there're quite necessary enough on the latter. I would put a 10µF immediately beside the expansion connector, and a 100nF ceramic immediately beside the SID with minimum conductive distance to the Vcc (+5V) and GND pins, plus a second one similarly between Vdd (+12V) and GND. These bypass capacitors are not shown in the SID datasheet's application diagram, but are mentioned in the text and are generally required by all logic ICs.

So I ended up getting it to work like the diagram in the data sheet. It turns out there was something wrong with the SID that I was using. I bought a new SID and and had better luck. Interestingly, I also tried a swinsid but that didn't work unless I NANDed the PHI2 to the $b000 line. It turns out the swinsid doesn't read the PHI2 line and that's why it has to be NANDed. It's possible the person who designed that other card knew this as well and designed their schematic to be compatible with both a SID and swinsid.

I wonder if there's some way to modify a tracker program to write to the locations where the sid is on the replica 1.