Hi everyone,

i tried to clone some functions of the mmu 8722 found in CBM 128.

This first attempt is just a try, and was not used in a real project, even if i plan to use it really for a test.
The attached archive is the project for xilinix ISE version 11.1 and the verilog source code is in clone_8722.v (device: xc95108-PC84, plcc 84 socket). Look at main module for explanation of in/out signal to the device.
Read initial comment in source code for some implementation notes. Of course any comment is appreciated.

Marco

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I'm not familiar with the 8722, so I can't comment on the overall functionality, but I would like to suggest a different style, that I feel is a bit easier to read. For example, the mx2e module could be written like this:

Or, since that module is only used once, you could even remove it, and put the code in-line. Also, lines like these:

Could be written as:

Which would make it easier to see at a glance that you've used the intended address.

Hi Marco,
I've just checked your "clone_8722" verilog code against the expected functions from a real 8722 mmu and, as you were looking for some good feedback, I'm going to provide you some.

First of all, there are some inconsistencies in referring to the MMU registers and so to naming the related identifiers in the code:

- you call "MCR" what is actually the "CR" register (i.e. $D500/$FF00)
- you call "CR" what is actually the "RCR" register (i.e. $D506)
- you call "PR" what is actually the "P0L" register (i.e. $D507)

Then, some MMU registers are missing or incomplete:

- "MCR" ($D505) : I/O register, whose signals should be hardwired to external ports (like you did for MC7..MC0, that are connected to the wrong $D500 register at the moment, see above)

- "RCR" ($D506) : bit0-1 the shared size can be 1K, 4K, 8K, 16K (not 1K,2K,4K,8K) and you should also consider bit3 (not just bit2) for shared ram position ("00"=none, "01"=bottom, "10"=top, "11" = both), bit6-7 (video bank, i.e. bit 16-17 for the VIC) should set CS0-CS3 when AEC is set low by VIC for a DMA cycle (so we can say that bit6-7 of either CR or MCR are the "emulated" A16-A17 for a C128 system, driving CS0-CS3 accordingly to AEC)

- "P0H" ($D508) : the "P0" register is split in 2 registers: "P0L" (implemented) and "P0H" (bit 16-19) that is unimplemented in your code (at least you have to implement translation up to bit16-17 for a 256K system)

- "P1L" ($D509) and "P1H" ($D50A) : the "P1" register split in 2 registers like for P0 (see above)

- "VR" ($D50B), I suggest filling its read-only bits (7-4 and 3-0) respectively with constants "0100" (BANK_VERSION=4 i.e. 256K) and "0001" (MMU_VERSION=1)

While "MCR" appears as an I/O register that doesn't relate to translation, I guess you'll want to implement it (and "VR" as well) as your code claims to be a "clone" of the original MMU8722. Moreover, there's an important address translation performed by the MMU when Z80 mode is active (bit0 of MCR=0) regarding Z80BIOS ($0000-$0FFF must become $D000-$DFFF as a Z80 - differently from a 6502 cpu - wants system ROM at the beginning of the available memory)

You can find a quick register reference documentation at http://www.oxyron.de/html/registers_mmu.html or a complete one at https://www.pagetable.com/docs/Commodore%20128%20Programmer's%20Reference%20Guide.pdf (page 530) and https://myoldcomputer.nl/Files/Datasheet/MOS8722.pdf

Again, some external I/O ports are missing:

- AEC (input) to disable address translation (three-stating the TA output, to avoid contention with the VIC) during DMA (when AEC is low)
- ROMBANKLO, ROMBANKHI, IOSELECT (output) to assert the current ROM configuration for the PLA 8721 in relationship to bit5/4, bit3/2, bit1, bit0 of the configuration register ($d500) and the address to translate (respectively for $C000-$FFFF, $8000-$BFFF, $4000-$7FFF, $D000-$DFFF)
- CS2, CS3 (output) in relationship to the bank select (bit 6/7) of the configuration register ($D500)
- Actual MCR bits ($D505) should be exposed (input/output) for the C128 glue logic to work (40/80sense, C64mode, EXROM, GAME, FSDIR, Z80EN), as said before

Finally, regarding your HDL implementation, I would advice you to implement a double port for cpu data (Din,Dout instead of D) and delete remaining unnecessary ports (what you call "CR0..7" are useless)

Let me know if this helps.

Still one note regarding the DBE signal...

You have implemented this input in order to (externally) manage contention on the cpu data bus when registers are read, still in a real 8722MMU there is not such a port and there isn't any external "chip select" detection logic for the MMU in a C128. So the best solution is that your verilog code accounts for this signal internally, that means to set the outgoing data bus to Z when the input address is not between $D500-$D50B or $FF00-$FF04.

Hi webmst,
this attempt to replicate some functions of the mmu-8722 in a xilinix chip was not intented to replace in full a real 8722.
In he past i tried some experiments with a real 8722 interfaced with a 65c02 but not for built a c128-clone. In fact i don't have interest on implementation of interfacing with VIC chip (i have my own vga board), nor interfacing with a Z80. More, i planned to use this clone mmu in a system without DRAM (so i lack CAS and MUX signals. and AEC also), without clock speed limitation.
I wanted just implement the banking-switching and the page-0 relocation, with the freedom to map i/o registers (for this reason access to internal registers is maded with DBE external signal).
In the real mmu-8722 is not possible to access additional 128K (of course can be done with two 8722 in parallel except some signals), and after reset this chip re-map first 4k to handle z80 bios that is not good for a only-6502 system. More, using a real 8722 is complicated by the generation of MUX signal and the fake CAS signals.
Anyway i never attempt to implement this mmu+65c02, and some tests with 8722+65c02 failed.

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Hi Marco, thank you for your reply.

I understand what you mean, still I had read your request for feedback as an intermediate stage to go for a complete implementation (a "clone" as you named it) of a real MMU8722, a chip that you showed to know pretty well and that - let me say - is an objective very close to the current state of the code.

On my side, I had found your MMU implementation while looking for a ready-to-use HDL of the MMU8722 to complete my C128 on FPGA design (so you can understand why I suggested you the above corrections, such as a 256K implementation, while I didn't care for having DRAM-like logic signals such as MUX and CAS); I suppose you can guess how much work this project is requiring for all the dedicated chips that - differently from a C64 - nobody cared to implement in a HDL.

Anyway, speaking about the 8722, if you aren't interested in finishing your implementation, I'll have either to improve my Verilog programming skills to complete it (VHDL is my HDL of choice) or to rewrite it from scratch; in any case it'll increase the amount of work still to be done.

If you change your mind, please let me know.

Hi webmast,

in last years my interest is migrated to 65816 projects (even if i builts two 65c02 projects: one is on my web site, the one other is based on a banked-scheme similar to the one used on the plus/4), so i lose interest on stricty 6502 uP.
If you want implement a fully 8722 in HDL the code i uploaded is a good starting point. In my implementation i let MCx & CRx lines to be freely used in the decoder side (the PLA must be implemented of course), but you can use in a way strict close to 8722; in fact in the 8722 MS0-MS2 lines reflect the bits of control register in a pre-defined address range. Hard-coding registers address in HDL make DBE line useless.
Anyway you can of course use this code how you want and you like; verilog is very closed to "circuital implementation", and i'm more comfortable thinking in term of logic and registers; in fact i developed this code starting from a classic circuit implementation: any verilog module have a schematic.

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Hi Marco,
as I wrote before, I had already analyzed your code in comparison to the behavior of a real 8722; what I didn't know was the purpose of your implementation and the kind of feedback you could have liked to receive (I had also checked your website, in order to understand your main interests; BTW I realized you are an old-school engineer who still likes to tinker with real hardware but I didn't fully understand why you didn't think of an FPGA implementation of your "C16" project as you can write Verilog code and this technology would have provided you the design flexibility and cost reduction you were already craving for at the end of the "MB01" project).

Your clone_8722.v source is very clean, but one thing is to be able to read Verilog and another is to be able to write it, especially if this means modifying existing code; so my only choice is between deciding to write it from scratch in VHDL or to get confident enough with Verilog to modify yours according to what I suggested before.

Hi Webst, as told, when i developed this code i planned to built a real 65c02 system. I uploaded this code for 2 raisons: 1) share with other peoples (in forum many threads about MMU for 6502). 2) Have feedback not just about verilog implementation, but especially about my approach to a possible MMU.
In 2017 i started some eperiments with a real 8722 (i have five chips) but i failed to get a 65c02 working like i wanted (too long now for explain why failed), so i started to develop an "8722' with discrete devices but soon the project become very complex (any preconfiguration register requires an 8-bt latch plus the buffer for read-back, and a mux is required to store the selected preconfiguration register to the configuration register, and so...). For this reason i started the verilog project: a schematic with latches and logic can be easily written in verilog (and xilinix ise itself can develop projects with schematic)
Meanwhile, as told, i losed interest in built a real system with this mmu (even if developed a full schematic), so this branch is in fact dead.

About your question: better work in existing verilog code or start from scratch in VHDL? I don't know VHDL language (just very little little), and verilog give the chance to easily connect primitives as in a real schematic development. If you are able to think at implementation in term of circuital blocks is better use verilog.

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Hi again Marco,
forgive me if I edited my previous post while you had already answered, we were writing almost simultaneously and I hadn't refreshed the page in the meantime for me to read your last reply.

Regarding your last note about a preference on Verilog/VHDL, I didn't mean to revive the HDL war of the last decade (both languages have their pros and cons, moreover they are equally supported by the main silicon producers and source codes can be mixed in the same project) and I wasn't speaking about a "philosophical" choice (quite abundant subject when debating retrocomputing); I simply meant I still have to pragmatically decide what it is best for me to do now in order to proceed with my FPGA project given the current status of the MMU implementation (the same has already happend with other components).

Good question. My goal was built a machine with a serious O.S. using old real chips (sentimentals matters). For example build a video card with vga-compatible output is really easy using a simple xc9572 device (but the hard part is the contention of video ram-buffer with cpu), or using some older vga chip as from Cyrrus Logic, but built with an older CRTC chip was much satisfactory (a proof of concept, if you prefer).

Anyway, what is you project in FPGA? Just a full 8722 replica? Or others chips too?

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