Hello, I'm looking to see if anyone has a schematic or tips for how to connect a sid chip to a replica 1 by Briel Computers. I've seen some projects that have attempted this on the replica 1 but there have been no posted schematics. If anyone has a suggestion it would be very appreciated!

Thank you!

I think my issue has to do with how I'm doing chip select. I have been tying the chip select pin of the directly to the $B000 pin on the Replica 1 in order to have it selected in that block of memory. This may be the incorrect way to do this but looking at the data sheet for the sid, it seemed like the chip select could be tied to the addressing directly without having to AND it with the clock signal or anything. Idk if anyone else has a suggestion for how to enable chip select for this.

Welcome, Rogers64!

How about sharing that datasheet with us? And a schematic for the Replica 1, too (without the SID I mean).

There are lots of competent people here who may feel inclined to help. But you'll get a better response if you make our job as easy as possible. Try to lay everything out for us so we don't have to go hunting for info before we even begin answering the question!

Cheers,
Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hey, thank you for the reply! I actually just managed to get it working! I looked closer at the SID data sheet and I do have to NAND $B000 with the PHI2 signal. The chip select can only trigger if the chip select is low, PHI2 is high, and RW is low. In this case I just tied RW low as we will always be writing to the SID when playing music. Sorry for the crude illustration, but this is how I connected it. Maybe this can help someone else whose interested in doing this with the Replica 1.

I have been thinking of adding support for 2 SID chips. I'll post a schematic for that if I get it working.

Hmm, I'm inclined to think you were correct when you said earlier, "it seemed like the chip select could be tied to the addressing directly without having to AND it with the clock signal or anything."

But why did the extra gates make a difference? It may be simply because you added some delay to the chip-select signal.

What happens when you do this?

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I could try it! It might be delay. But the data sheet did say that the clock cycle has to be high when the CS is low so that's why I did it this way.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

http://archive.6502.org/datasheets/mos_6581_sid.pdf
here' the link

Thanks! And if you try that experiment pls report back.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

So I tried running it through two inverters, but it didn't seem to react. I configured it back to how I had it and it worked again.

Well, I'm glad you're having some success at the moment, but I have an uncomfortable feeling it won't be long until you're back with some other issue.

I need to frankly (and gently, I hope) mention that the stuff you're reporting sounds very fluke-y -- and I say that as a person who's created his own share of fluke-y situations in the years and decades past! All part of the learning curve, eh? But my spider sense warns me that you don't presently have a good grasp of how 65xx peripherals and their control inputs are supposed to work. (I myself have never used a SID but all peripherals intended for the 65xx environment have a great deal in common -- and I'm aware of none that requires chip-select to be gated with Phi2. Furthermore the "Typical Application" schematic in Appendix C of the datasheet you linked shows no such gating. You would do well to follow that diagram closely.)

I haven't seen photos of your setup, nor have I done a web search to look into the Replica 1. What CPU is in that thing? Is there a schematic you can share? If you require further assistance then please supply us with what we need in order to notice aspects and details you may have missed.

Have fun and keep in touch,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Here's a CAD Schematic for the Replica 1.

I went back online and found someone who connected a SID to a real apple 1. I say real but i think it's actually a 1 to 1 clone of the apple 1 unlike the Replica 1. And by looking at it they did the same thing I did by gating PHI2 with the address lines.

I'm not saying what s/he did can't possibly work. Nevertheless, my advice is to stick closely to the "Typical Application" schematic in Appendix C unless there's a concrete reason to deviate. I'm not convinced there is, but hey -- who knows.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html