Hello!

I've designed a 6502 SBC with a 2864 and a 6850 UART. I'm having trouble getting the 6850 to do anything correctly. For starters all I have is a program that resets the 6850 and reads the status register repeatedly. I verified that the 2864 works (the 6502 runs a small loop program), and that it is not selected when accessing the 6850 (/CE is high for the one cycle, but /OE is low--shouldn't be a problem).

I'm resetting the 6850 by writing the master reset to the control register and then immediately writing the regular control word to it. E is driven by phase-2, and the chip enable is driven during the entire read cycle. When I read the status register, I get low levels for D0-D5, but D6 is high during the first half of the cycle, while D7 is high during the second half. It's really strange.

I thought the 2864 might be outputting data at the same time, but it doesn't seem like that's the case, as its /CE is high during the read and the address in the 2864 contains the byte 00.

Anybody with any experience with the 6850 have any ideas? I'd appreciate some help!

Oh, in other tests, I've commanded the 6850 to transmit characters repeatedly, or even just a break, with no luck.

Scott

> I'm resetting the 6850 by writing the master reset to the control
> register and then immediately writing the regular control word to it. E is
> driven by phase-2, and the chip enable is driven during the entire read
> cycle. When I read the status register, I get low levels for D0-D5, but
> D6 is high during the first half of the cycle, while D7 is high during the
> second half. It's really strange.

You may have already checked these, but here it is anyway. It may benefit someone else.

By "the first half of the cycle," I assume you mean when phase 2 is down. If so, perhaps there's a glue logic error because, with a few execptions that don't usually exist in small home-made computer boards, nothing should be putting data on the data bus during that time. Everything should be high-impedance, and the parasitic capacitances should just hold the last logic states from when phase 2 was up. The R/W\ , register selects, and chip selects have to be valid a minimum amount of time before the E (phase 2) goes up. Is it possible a couple of pins got crossed in the wire-wrapping? Is there a good reason Status<7> (interrupt occurrence bit) is already set? According to the data book, it doesn't look possible to have bit 7 is set while bits 0 through 6 are clear, which is another reason to suspect a wiring error. Otherwise, are you sure the IC is good? Does it work in another circuit? If it could have been damaged with static, do you have another one to try to see if it behaves the same in your circuit? When you read out high and low levels, are the voltages reaching close to 0 and +5V? (In-between levels could indicate bus contention or that a power or ground pin someplace didn't get connected.)

> Anybody with any experience with the 6850 have any ideas?
> I'd appreciate some help!

No 6850 experience here, just a Mot data book and 65xx and other experience. Why not use the 6551 with the on-board crystal oscillator and baud rate generator?

Garth

Thanks for the help, Garth. I found the problem; I had the addresses for the two 6850 register locations reversed. When I tried to do a "master reset" I was unwittingly writing to the transmit register. I even wrote a simulator for the 6850 to test my software on, but of course the addressing was wrong there, too. Lack of a true master reset explains why D7 was high (INT bit with no interrupt conditions).

I did drive the 2864 /OE during the entire cycle because the 6502 data sheet (Synertek) requires data valid for 10 ns after phase-2 low, while the 2864 sheet guarantees 0 ns after /OE high. This explains why D6 was high for the first half (phase-2 low) due to capacitive effects from the previous read cycle, and low for the second half when the 6850 actually drove the bus.

I've changed the glue logic so that phase-2 high activates /OE (NAND with R/W). Luckily this was just one trace cut and one blue wire on my 7400, which also adds some delay to keep /OE high a few nanoseconds past phase-2 low.

I probably would have chosed the 6551 since it actually belongs to the 6502's family, but I already had a few 6850 chips before I found out about the 6551.

Hi Schidester,

The 6850 is a reliable chip. I used it a long time ago
with interrupt driven TX and RX and I didn't find
any problems.

Cheers,

Paul