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PostPosted: Thu Dec 31, 2020 10:42 am 
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One thing that would be handy in some of my experimentation is to be able to use multiple select lines out of a typical 74'138 setup without needing to add further gates to the system. As any example, the 6502 SBC I use has decode from a '138 for each 4K block from $8000 to $F000, and $8000 to $CFFF is unused address space. If I want to connect an off-board 16K RAM chip to it, I need at least four gate inputs to do that from the '138, or three from the address lines assuming I use $8000, whereas if I had open-collector selects I could just wire them together to the chip select and drop a pull-up on that line.

Sadly, there doesn't seem to be an open-collector version of the '138, though there are similar demuxes with open collector versions, such as the '156. (Annoyingly, though, with the latter wired for 3→8 decoding, you lose a select input over the '138.)

That got me to thinking, I've never actually seen an open-collector decode circuit with pull-ups for doing chip select. Is this a common technique for chip selects and I've just missed it, or is there some reason that it would be a bad idea?

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PostPosted: Thu Dec 31, 2020 12:32 pm 
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Mmm, I would suspect getting the rise time within reasonable bounds needs a smallish pullup resistor, which in turn will dissipate static power. (But, only when the signal is low, which is rare. So perhaps it'll be fine?)


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PostPosted: Thu Dec 31, 2020 1:09 pm 
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BigEd wrote:
Mmm, I would suspect getting the rise time within reasonable bounds needs a smallish pullup resistor, which in turn will dissipate static power. (But, only when the signal is low, which is rare. So perhaps it'll be fine?)

Yeah, there's never more than one select low, and usually the more frequently used ones, such as main memory, are decoded directly by A15 or whatever and so not all selects would use pull-ups.

My understanding is that 4K7 is considered a fairly low pull-up value, and even that's only going to consume a milliamp or so, which is not terribly significant in my NMOS world where a 74LS138 draws 7-10 mA (if I'm reading the data sheet correctly) and the CPU can easily be drawing 100 mA or more. (ISTR my NMOS 6502s were drawing about 110-120 last time I measured one.)

(Obviously I'd be doing things differently if I were looking to build a battery-operated device, starting with using CMOS everywhere, but that's not the case for my early-80s-microcomputer level of technology.)

So I think it's really more just about the time constant of the RC circuit introduced by having a pull-up resistor, right? Or is there something else about this that I'm missing?

I should mention, I'm mainly working at 1-2 MHz clock speeds, though going up past that to as much as 5 MHz might well happen on some boards.

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PostPosted: Thu Dec 31, 2020 1:17 pm 
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I suspect it is about the time constant, which will vary according to the load - the pull up needs to be adequately fast in the most highly loaded case. If the loads are TTL, they will sink current statically too, which again pushes for a smaller pullup. (Just possibly, there would be noise concerns with a slow rise time, even if it met the timing spec, because it's an opportunity for trouble as the voltage crosses the threshold.)


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PostPosted: Thu Dec 31, 2020 2:17 pm 
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cjs wrote:
Sadly, there doesn't seem to be an open-collector version of the '138, though there are similar demuxes with open collector versions, such as the '156. (Annoyingly, though, with the latter wired for 3→8 decoding, you lose a select input over the '138.)
'145 -- as used in the KIM-1, IIRC :mrgreen: -- is another option. It's a 4-to-10, but can also be applied as a 3-to-8. (Outputs 8 and 9 become no-connect, and the Most-Significant select input serves as active-low Enable.)

Another "Open Collector" one-of-eight option is to use a FET switch based mux / demux such as 4051, the much faster 74HC4051, or the even faster (but still 4051 pin-compatible) MAX4617 or something similarly modern. Pin 6 is an active-high enable for the 4051-type switches, and pin 3 can be used as an active-low enable.
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Regarding the use of Open-Collector logic in general: yes, you'll typically be faced with an unhappy tradeoff between rise time and the amount of power wasted in the pullup... (or pulldown -- the FET switch based product are equally happy transmitting active-high signals).

:arrow: The performance vs wasted power tradeoff moves to a much happier place if the pullup (or pulldown) resistor is replaced by an active current source (or sink). More on this here. This is also useful when the pullup is used as a form of level shifting -- ie, when a TTL (or similar) device needs to drive an input that expects CMOS voltage levels.

Finally, looking back to the original suggestion of gating together a few outputs of an ordinary '138, remember to consider the very small and VERY fast (3 ns max :shock: ) gates described here.

-- Jeff

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PostPosted: Thu Dec 31, 2020 8:19 pm 
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cjs wrote:
My understanding is that 4K7 is considered a fairly low pull-up value, [...] So I think it's really more just about the time constant of the RC circuit introduced by having a pull-up resistor, right?

Suppose you have 20pF of capacitance for the 4.7K to charge up. 20pF x 4.7K makes for a 94ns time constant for the rise time! Replacing the resistor with a current mirror as Jeff suggests will help somewhat. So suppose you give it a constant 1mA. Then bringing it up by 3V will take 20pF*3V/1mA=60ns. Still bad, but not as bad. It'd be better to just use the proper gates with totem-pole outputs.

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PostPosted: Thu Dec 31, 2020 11:29 pm 
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Thanks, Garth -- you're right; in some ways I was over-enthusiastic in my endorsement of the current source.

By way of followup, it's noteworthy that in Garth's example he specified the threshold he's shooting for (3V). If the target voltage were higher then the current source would offer even better power/performance tradeoffs, increasingly outclassing the resistor; conversely, for lower target voltages the resistor is at less of a disadvantage, offering power/performance tradeoffs almost as good as those of a current source. Of course, lower input-voltage thresholds are generally associated with TTL rather than CMOS, and I'll come back to that point later.

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20pF x 4.7K makes for a 94ns time constant for the rise time!
Yup -- and 4.7K is a reasonable example if we need to be cautious about power consumption. But if we don't then pullups like 1K or 470 ohms become feasible, slashing the time constant by five or ten. I'm just highlighting the tradeoffs that're available. And yes for 470 ohms you'll wanna check if the '138/whatever is capable of sinking 10 mA (several logic families are).

Open Collector logic is certainly a dated concept but it may be attractive, depending on circumstances. Sometimes Open Collector logic "just fits"... or, it may be the case that you can save a lot of trouble by the strategic use of a diode or two. :twisted: :!: Either way, if I were whipping up such a circuit I'd try to arrange that the chip receiving the signal be 74ACT or AHCT type (not 74AC or AHC). The lower input threshold means a plain ol' resistor pullup will probably perform satisfactorily.

-- Jeff

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PostPosted: Fri Jan 01, 2021 1:45 am 
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Dr Jefyll wrote:
Thanks, Garth -- you're right; in some ways I was over-enthusiastic in my endorsement of the current source.

I was a little disappointed myself to see that although the rise time improvement was substantial, it was not nearly enough to get it down into the sub-30ns range. More current would help of course.

Quote:
By way of followup, it's noteworthy that in Garth's example he specified the threshold he's shooting for (3V).

Actually I was thinking of the source at 0.4V (from LSTTL outputs), and bringing it up to 3.4V, which is close to the 70% of Vcc which CMOS generally likes.

Quote:
Quote:
20pF x 4.7K makes for a 94ns time constant for the rise time!
Yup -- and 4.7K is a reasonable example if we need to be cautious about power consumption. But if we don't then pullups like 1K or 470 ohms become feasible, slashing the time constant by five or ten. I'm just highlighting the tradeoffs that're available. And yes for 470 ohms you'll wanna check if the '138/whatever is capable of sinking 10 mA (several logic families are).

Hopefully there are no non-CMOS inputs; but if there are, like TTL or LSTTL, make sure you include their low-state input current in the budget, to make sure the driver can pull down hard enough.

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PostPosted: Fri Jan 01, 2021 3:43 pm 
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I don’t think the sink current is going to be a problem for a 74LS145, see the datasheet.

Open collector outputs that are designed to drive relatively large loads (for a logic gate chip) should be able to cope with pull-ups as low as 330Ω no problem.

If however you are using diodes on the outputs of normal logic chips (‘standard’ outputs for that technology), then use something like a BAT85 (or equivalent) and you should be careful if your pull-up resistor is lower than 680Ω. 680Ω being the lowest standard E12 series value that is okay for a standard 74LS gate output.

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PostPosted: Fri Jan 01, 2021 7:01 pm 
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1024MAK wrote:
I don’t think the sink current is going to be a problem for a 74LS145, see the datasheet.

Open collector outputs that are designed to drive relatively large loads (for a logic gate chip) should be able to cope with pull-ups as low as 330Ω no problem.

Pete (forum member "saipan59") had suggested it near the end of the "Tip of the Day" column (20 years ago—Wow, time flies!), but I was forgetting how strong those outputs were— definitely a lot stronger than most 74LS parts' outputs! They're awfully slow though, specifying up to 50ns of propagation delay (both directions) with a 100Ω pull-up resistor. Still, it's a good part to keep in mind for the right uses.

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PostPosted: Sat Jan 02, 2021 1:10 am 
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The other option if it helps with the logic, is to use a 74xxx238 instead of a 74xxx138. The 74xxx238 has positive logic (non-inverting) outputs.

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PostPosted: Sat Jan 02, 2021 4:33 pm 
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GARTHWILSON wrote:
Dr Jefyll wrote:
...then pullups like 1K or 470 ohms become feasible, slashing the time constant by five or ten.... And yes for 470 ohms you'll wanna check if the '138/whatever is capable of sinking 10 mA (several logic families are).
Hopefully there are no non-CMOS inputs; but if there are, like TTL or LSTTL, make sure you include their low-state input current in the budget, to make sure the driver can pull down hard enough.

Well, first of all there are almost certainly non-CMOS inputs: I'm doing systems typical of early '80s microcomputers (i.e., 74LS family), remember.

As it turns out, checking the sink current is definitely a good idea. I had assumed that open-collector parts could always sink relatively large amounts of current, since all they need do is short the output to ground, but a look at TI's 74LS05 datasheet indicates that the LS part is recommended to sink no more than 8 mA. (The 7405 can sink up to 16 mA.) I had assumed that most open-collector parts were designed more like the 74LS06, which can sink 40 mA.

GARTHWILSON wrote:
Pete (forum member "saipan59") had suggested it near the end of the "Tip of the Day" column (20 years ago—Wow, time flies!)

Oh, that's worth quoting here, because it's from someone who actually did exactly what I'm wondering about:

saipan59 wrote:
For address decoding on a not-real-fast design, try using a 74LS145 instead of an LS138. the '145 has open collector outputs, which means you can "wire-OR" the outputs to change the memory mapping....

This approach was hotly debated some months ago in the "PCB project" discussion. Because there is no active pullup on an O.C. signal, the signal integrity may not be good enough for higher clock speeds. What is "higher"?? Well, it depends on several things, such as the value of the pullup resistor, the loading on the signal, etc. I've used this approach at 1.84 MHz with no problems, and it should work at 2 or 3 times that speed.

So, basically, it sounds as if what I want to do should work at the speeds I'm using.

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