Using FM1808 as RAM

[cjs]

GARTHWILSON wrote:

The numbers probably had to do with individual bytes....

Ah, good thought, though it actually turns out to be 4-byte rows in the FM1608, so that tight loop checking for the next character from the serial port is still going to wear out that row pretty quick if you leave your machine sitting there at the prompt for hours on end.

Quote:

Regardless, Jeff's data sheet says the number is unlimited now though, just like SRAM.

Sadly, I am doubting that my FM1608s magically received this upgrade.

More seriously, one does have to pay a bit of attention to part numbers. I have just found an FM1808 datasheet dated one month after the FM18L08 datasheet attached above which says that the non-L part still has 10^12 read/write cycles endurance. So I guess they were manufacturing both at the same time.

[Windfall]

cjs wrote:

Windfall wrote:

The datasheet I have (Rev 2.3, May 2003) says 'High Endurance 10 Billion (10^10) Read/Writes'. I kept track of this for a while, back then, and I think the endurance increased by a factor of 10 or so in just one or two years (although I'm not quite sure if I have kept the earlier or later datasheet).

Am I calculating this wrong, or is 10^10 incredibly low to me for anything anybody would consider using as system RAM or ROM, especially if running code from it?

An access doesn't wear out the entire chip. It only wears out a 4 byte chunk of it. Or, as the datasheet puts it :

Each read or write access causes an endurance cycle for an
entire row. In the FM1808, a row is 32 bits wide. Every 4-
byte boundary marks the beginning of a new row.

[Windfall]

cjs wrote:

though it actually turns out to be 4-byte rows in the FM1608, so that tight loop checking for the next character from the serial port is still going to wear out that row pretty quick if you leave your machine sitting there at the prompt for hours on end.

You definitely have to keep that in mind when using the limited endurance FRAMs ... If you really really really can't move a tight, often executed loop to outside the FRAM, you may want to consider unrolling the loop to distribute the wear across more 'rows'.

[Chromatix]

With the older types, I think the anticipated use cases are for data that needs to be written frequently or even continuously, but not millions of times a second - and certainly not as main system RAM for a microcomputer. Examples might be for data logging (think "black box" survivable memory where the last few seconds of data might be the most valuable), or for an EEPROM replacement for convenient updating during development, in the case where the contents will be shadowed to SRAM before intensive use (which would still be done with the EEPROM because the latter is slow). It could also be used as a small filesystem, though something like an SD card would be a lot more capable in that respect.

Edge cases would be to keep the user's documents in while they work, so that they would be recoverable in the case of power loss, even though the computer itself has to bootstrap "normally". That doesn't require a huge number of read or write cycles while idle, only when the data is actually processed or updated.

The new type with "unlimited" endurance could be used in the same way as the ferrite-core memories of old, whereby program code and data alike remain present across power cycles. This requires a new approach to bootstrapping the machine, since the CPU state itself remains volatile. However, if impending power failure can be detected while VCC can still be maintained for some short period of time, the CPU can do some housekeeping (such as calculating a checksum over the data as an assurance that the memory contents are valid) that would simplify that task.

[Michael]

I ran across a small cache of "new old stock" 8Kx8 nvRAM chips that I thought were interesting in that they support unlimited reads and writes to RAM and they 'recall' and 'store' data to and from the RAM and EEPROM cells during power-up and power-down.

Stay safe. Happy Holidays and cheerful regards, Mike

[bartleph]

Windfall wrote:

bartleph wrote:

SRAM pins:-
27(/WE) RamRW
22(/OE) RomOE
20(/CS) A15
RamRW is derived from /CPURW NANDED with Phi2
RomOE is derived from CPURW NANDED with Phi2

You cannot use A15 as a chip select for reasons that have been highlighted already, several times. A15 can remain 0 or 1 for many cycles and therefore does not make the required transition to act as the 'address valid' strobe that FRAM needs it to be. You need to work Phi2 into /CS, e.g. /CS = /A15 NAND Phi2.

Just wanted to say thanks Windfall for sorting my issue. I got real cocky, and replaced the EPROM with a programmed FM1808 as well. Works perfectly and means I can modify my firmware without having to erase and re-blow the EPROM..
Paul