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PostPosted: Sun Dec 06, 2020 10:33 pm 
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At the very least the PIA and VIA datasheets are wrong about Voh; they are proper CMOS devices with totem poles that can drive rail to rail with an impedance of about 50 ohms (ie. at least as hard as 74HC). The exception is that on the -N devices, the GPIO pins are built as NMOS constructs, specifically for maximum compatibility with existing applications. On the -S devices, the GPIO pins are also strong CMOS totem poles, with the addition of "pin keeper" devices.

I think we also have documented cases of a W65C02S being simply plugged into an existing vintage machine with 74LS glue logic and NMOS memories, with the only "mod" required being to bend up the /VP pin which is a GND on the original NMOS devices. Technically one should also ensure RDY has an explicit pull-up on it. That would indicate that most if not all of its inputs are actually TTL compatible, even if they are specified as CMOS inputs, at least at modest clock speeds (NMOS 6502s went up to 3.5MHz maximum, most vintage machines ran them much slower than that for various reasons).

However, it is safest to assume that CMOS level inputs are required, especially if you are aiming for relatively high speeds, and to ensure that your clock signal is strong and clean with fast edges, and to make sure you have enough power supply bypassing near each IC's power pins.


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PostPosted: Sun Dec 06, 2020 10:36 pm 
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fachat wrote:
Looking at the datasheets from the W65C21S and the W65C816S. I wonder how they would actually work together - they are not compatible Voltage-wise if I read it correctly...:

1. The Input High Voltage Vih on the W65C816S for e.g. the data bus is min VDD x 0.8, i.e. 4V for a 5V supply. Voh on the '816 isn't even documented at all.
2. The Output High Voltage Voh on the W65C21S for the data bus is 2.4V min. Vih is 2.0V

So, if the '21 just delivers 2.4V on the data bus, the '816 would not reliably read it.

Similarly the difference between the W65C22S and W65C22N - here both specs are even on the same page.
1. Voh on the "N" is 2.4V. Vih is 2.0
2. Voh on the "S" is not documented. Vih is VDD x 0.8.


Hm. Not sure what to make of it. My guess is, that the Vih on the '816 is wrongly documented, what do you think? What would it be really?

I am of the opinion that the 65C02's and 65C816's inputs are TTL-compatible. This would have to be true for the 65C02, as WDC has long touted it as a replacement for an NMOS 6502. Replacement of the 6502 with 65C02s in PETs and other Commodore machines prior to the C-64 was routine at one time. As NMOS 6502 systems were largely built with 74, 74S and 74LS logic, the 'C02 would not have been stable in such an environment if VIH had to be VDD × 0.8, a level that most TTL logic cannot achieve without pull-ups on their outputs.

Furthermore, both the EPROM and SRAM I have used in my POC units are specified as producing TTL-level outputs. POC V1.2 is running solidly at 20 MHz with those parts. I seriously doubt that would be possible if the 816 insisted on CMOS logic levels at its inputs.

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PostPosted: Mon Dec 07, 2020 5:04 am 
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fachat wrote:
Looking at the datasheets from the W65C21S and the W65C816S. I wonder how they would actually work together - they are not compatible Voltage-wise if I read it correctly...:

1. The Input High Voltage Vih on the W65C816S for e.g. the data bus is min VDD x 0.8, i.e. 4V for a 5V supply. Voh on the '816 isn't even documented at all.
2. The Output High Voltage Voh on the W65C21S for the data bus is 2.4V min. Vih is 2.0V

In the Aug 2010 W65C21C/N data sheet, what I'm seeing for VOH is VDD-.4V @ typically 10mA, @ 4.5V VDD. It should be even slightly better at 5V.

WDC's data sheets have a history of errors, which is why if you really want to know something, you just have to try it; but fortunately the actual parts are usually much, much better than the specifications let on. I have done some brief tests on the W65C816S's pin drivers. Their behavior was pretty much symmetrical, able to pull up to VDD just as hard as they can pull down to ground, unlike TTL which cannot pull up as hard. If you had to boil my test results down to approximations and treat the circuits as just a resistance, the data pin drivers acted very roughly like a SPDT switch with 50Ω in series with the common terminal (ie, the output); and the address bus pins, as a SPDT switch with 60Ω in series.

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PostPosted: Mon Dec 07, 2020 5:47 am 
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GARTHWILSON wrote:
...fortunately the actual parts are usually much, much better than the specifications let on.

I can vouch for that.

Although I cannot directly reveal my sources, I recently learned that all current WDC production parts are tested at 20 MHz. Note that this applies to parts with 6T in the part number, 6T meaning the part's die was produced in the TSMC foundry with a 0.6µ geometry. While such testing doesn't absolutely guarantee operation at that speed under every possible condition, it's a safe bet your 65C02 or 65C816 contraption will run that fast if it is equipped with sufficiently fast glue logic, is powered at five volts and was built using sound construction techniques.

TSMC started producing wafers for WDC in 2006. Prior to the use of TSMC, Sanyo produced wafers for WDC. Parts with their silicon were marked 8 or 6 after W65CxxxS, such as W65C02S6P-14. Sanyo 0.6µ wafers were produced from 2002 to 2006, followed by the switch to TSMC.

I recently received two Sanyo 0.6µ parts for testing in POC V1.2, the goal being to determine if they will run at 20 MHz. Incidentally, the current FMAX vs. VDD datasheet graph applies to all 6T parts, which is everything produced from 2006 onward.

WDC also change packaging vendors in 2005. Parts made prior to then were ink-marked. Subsequent production is laser-marked and therefore more difficult to counterfeit. 65C816s in PDIP with date codes starting with "20" have been produced.

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PostPosted: Mon Dec 07, 2020 7:20 am 
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I'm actually not concerned with the output stage of the WDC devices.

I need to know whether the input stage is "LVTTL" compatible or not. Being LVTTL would allow easy interfacing of 5V 65xx devices with 3.3V CMOS glue logic. It would be unfortunate, also for WDC, to have not thought of that.

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PostPosted: Mon Dec 07, 2020 1:34 pm 
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Again, can't you just run the WDC parts at 3.3V? They are specified for that, and that would save you an awful lot of hassle. That's what I meant by treating voltage level shifting as a distinct function, and putting it in only one place.


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PostPosted: Tue Dec 08, 2020 8:13 pm 
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Chromatix wrote:
Again, can't you just run the WDC parts at 3.3V? They are specified for that, and that would save you an awful lot of hassle. That's what I meant by treating voltage level shifting as a distinct function, and putting it in only one place.


I could. But all of the "externally visible" I/O needs to have 5V: IEEE488. Userport. Tape Port. And those are directly connected to the VIA and PIA, and you cannot know which direction (in or out) some smart designer has used on which pin.

So, VIA/PIA need 5V -> CPU needs 5V -> I need a voltage converter CPLD -> WDC.

Fortunately it is only Phi2, and the data bus that needs that. Phi2 can work with the method I found in the Xilinx application note, the databus can handled by a 74HCT245 (TTL inputs can be driven by both 5V and 3.3V CMOS, and CMOS output to 5V from the rail is acceptable for the CPLD). So I think this is the least costly way. And in fact "in only one place" :-)

RAM will probably then be 3.3V as well (as it's only connected to the CPLD) - 5V ROM needs TTL inputs, as upper address lines are driven by CPLD directly.
(But I may replace the parallel ROM with an SPI Flash at some point in time).

André

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PostPosted: Sun Dec 13, 2020 5:45 pm 
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Anyway, I have used the contact form on the WDC web site to ask about the datasheet inconsistency, will have to see if/when I get a response.

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PostPosted: Sun Dec 13, 2020 6:18 pm 
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fachat wrote:
Chromatix wrote:
Again, can't you just run the WDC parts at 3.3V? They are specified for that, and that would save you an awful lot of hassle. That's what I meant by treating voltage level shifting as a distinct function, and putting it in only one place.


I could. But all of the "externally visible" I/O needs to have 5V: IEEE488. Userport. Tape Port. And those are directly connected to the VIA and PIA, and you cannot know which direction (in or out) some smart designer has used on which pin.

So, VIA/PIA need 5V -> CPU needs 5V -> I need a voltage converter CPLD -> WDC.

Fortunately it is only Phi2, and the data bus that needs that. Phi2 can work with the method I found in the Xilinx application note, the databus can handled by a 74HCT245 (TTL inputs can be driven by both 5V and 3.3V CMOS, and CMOS output to 5V from the rail is acceptable for the CPLD). So I think this is the least costly way. And in fact "in only one place" :-)

RAM will probably then be 3.3V as well (as it's only connected to the CPLD) - 5V ROM needs TTL inputs, as upper address lines are driven by CPLD directly.
(But I may replace the parallel ROM with an SPI Flash at some point in time).

André


This whole level-shifter from 3.3 to 5v and back again has been a "solved-thing" in the Raspberry Pi world for a good number of years now. One way is easy, but bi-directional isn't much harder - A quick check from my local hobby electronics store finds:

https://shop.pimoroni.com/products/spar ... ut-txb0104

but there are many many other devices.

-Gordon

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