Chromatix wrote:
Again, can't you just run the WDC parts at 3.3V? They are specified for that, and that would save you an awful lot of hassle. That's what I meant by treating voltage level shifting as a distinct function, and putting it in only one place.
I could. But all of the "externally visible" I/O needs to have 5V: IEEE488. Userport. Tape Port. And those are directly connected to the VIA and PIA, and you cannot know which direction (in or out) some smart designer has used on which pin.
So, VIA/PIA need 5V -> CPU needs 5V -> I need a voltage converter CPLD -> WDC.
Fortunately it is only Phi2, and the data bus that needs that. Phi2 can work with the method I found in the Xilinx application note, the databus can handled by a 74HCT245 (TTL inputs can be driven by both 5V and 3.3V CMOS, and CMOS output to 5V from the rail is acceptable for the CPLD). So I think this is the least costly way. And in fact "in only one place"
RAM will probably then be 3.3V as well (as it's only connected to the CPLD) - 5V ROM needs TTL inputs, as upper address lines are driven by CPLD directly.
(But I may replace the parallel ROM with an SPI Flash at some point in time).
André
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