Hi there,

I'm building a new 65816 system and I found that I had an instability and looking around with the scope I see what I can only interpret as a glitch on VPA:

What I see is that VPA goes high for a short peak _during_ phi2 high!
In my understanding and according to the datasheet, VPA should stay constant during Phi2 high.

That peak on VPA results in a peak in the ROM select line, which is way too short, resulting in a failed read, and CPU crash.

Some info on that system:
- 8 MHz clock
- all logic is in a CPLD, VPA is input to the CPLD
- phi2 clock stretching to handle slower ROM access

I know that's not much info, I may be able to upload some scope screenshots later.
But has anyone seen this before?

Many thanks!

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

So here's a scope shot from the VPA in relation to the phi2 clock (see attachment).

As you can see there is a glitch on VPA while Phi2 is high.
Phi2 is stretched on the accesses before the glitch, as they go into the ROM, which is too slow for 8MHz, so it gets two cycles.
(stretched clock as RDY s*cks on the 65816, as it drives data bus even if RDY is pulled, so it pulls against the ROM when Phi2 and RDY are both low)

Trigger is on VPB (as external input, so not seen here), which is a further couple of cycles to the right, so we see what happens just before the CPU crashes,
which happens about every 10-60 seconds.

Anyone has seen this before?

BTW: it's about this "MicroPET", here's the last of three videos about it: https://youtu.be/HzObaa2JXKU Code will be on github once I have the CPU stable...

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

The glitch seems to happen in the data transfer phase of a STA $010000,X - so it _should_ actually be VDA=1 and VPA=0 here.

I have been looking at the supply voltage - does not look too bad. I increased VCC by 0,1V, that actually made the glitch appear more often it seems.

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

From further measurements I _think_ it could be because the CPU thinks there is another clock cylce, misinterpreting some wobble on phi2?

What do you think when you look at the attached picture, that shows the short ROM select, and the Phi2.
As you can see the CPLD is 3.3V, but 5V tolerant (A Xilinx xc95288xl, the best what I could get to still work with traditional TTL).

And if so, what could be the solution? Wire two CPLD outputs together to increase driving power on the signal?
After all, the I/O (2xPIA, VIA) need to go there also (in the future, not yet soldered in)

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

This is interesting, and worrying, if these signals are not stable between clock cycles.

As your images have suffered from orientation problems in the previews, I've tried to reattach them:



(I think if you put the images through any kind of JPEG converter, the orientation will get sorted out.)

Actually, isn't it important to give the '816 a full-rail clock? So, if using a 3v3 glue logic, it might be necessary to condition the clock through a 5V driver (and just possibly with a Schmidt input)

Very good point! I looked up the specs and indeed Input High voltage minimum is 0.8xVDD - which is 4V, so I'm running out of spec!

Luckily my (dev) board has a jumper to switch CMOS VDD from 5 to 3.3, and it now seems to run reliably

But that leaves me with another problem - If the CPU is 3.3V, the VIA and PIA need to be 3.3V also, so how do I handle 5V compatible I/O?
I'm ok with 3V high output from 3.3V CMOS, TTL isn't much better if at all, but input needs to be able to accept 5V...
Are the VIA/PIA tolerable? I'll have to look it up.

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Looked it up. No go. Both are "Pure CMOS", allow input high voltage only up to VDD+0.3V.

For 3.3V it seems it also has to be the "S" variant, "N" is only spec'd for 5V... need to check my inventory...

The only real concern on my current dev board is IEEE488. My current dev board has MC3446 as IEEE drivers, that output max 3.7V - so I'll go with that risk.
But as MC3446 are basically unobtainable (i.e. pricey), I wanted to use 74LS640-1 that are capable to pull IEEE-spec 48mA, but input would have been direct....
And for a really usable board I know many ppl who would want to have 5V on the tape / userport.

So, the next version will have 5V 65xx parts, and bus drivers between the CPLD and the 65xx world. Board is already tight, but maybe I then quickly go from 8-bit-parallel ROM to an SPI boot ROM.
That takes way less space, but I have to see if the SPI driver still fits into the CPLD.

(should I open up a new thread for the MicroPET?)

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Is that actually true? At a second look at this line from the datasheet (see attached screenshot from https://pdf1.alldatasheet.com/datasheet ... C3446.html )
I think the 3.7V max applies to the bus side ("B"), while the "R"eceiver output does not have a max rating....

I guess I have to measure it on my PET...

Edit: Bummer. It outputs nearly 5V.

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Possibly you can use an Atmel part for your glue, and run everything at 5V?
@hoglet noted elsewhere the "ATMEL 5V CPLD, such as the 128 macro cell ATF1508AS"

If you're running your glue logic at 3.3V, you should also run the CPU and other stuff at 3.3V, unless you have explicit level shifting logic between voltage domains.

The problem I have is that I need 5V I/O, but only have a 5V tolerant CPLD running at 3.3V from Xilinx. Altera does not support their old 5V CPLD with current downloads / new software installations anymore, which I had to learn the hard way (I can only program pre-built binaries but not code/create new binary images to be loaded into the CPLD)

Anyway, I managed to find an application note from Xilinx on how to drive 5V signals from a 3.3V device.

First approach was to use a 1k pullup on Phi2. And I can actually bust the myth that the WDC65816 needs clock rise/fall times of 5ns
(actually I don't think it's according to spec, but in fact the system worked as you can see on the screenshot.
Note that even the short spikes work - I have short cycles (not accessing ROM) and stretch the clock to long cycles when the ROM is accessed)

Second approach is an interesting one - the CPLD can use the pin as INOUT, and drive the signal as long as it senses it as low itself, and only leave the rest
to the pullup. That works actually quite well as you can see in the second screenshot.

It's not clear why this is still not going up to full 5V, but anyway, the system is stable.

However, I'm still running from ROM, and not reading from RAM, which goes through the CPLD, and this affects the data bus too.
Depending on setup times Databus may not be as critical as phi2 is, but I will see.

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

There are a couple of solutions depending on specs of course, that work with no or just simple logic. For example there ARE combinations where a 3.3V output can drive a 5V device's input.

See e.g. here https://www.xilinx.com/support/document ... /ug445.pdf "Driving 5V with a CPLD" or here https://hackaday.com/2016/12/05/taking- ... -shifters/

The only things is: read the specs first. very carefully. (as I did not...)

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

As I said, "explicit level shifting logic between voltage domains". You need to isolate that as a specific function, so that is where you can focus your reading of detailed specifications, and run everything within each voltage domain at that voltage. Otherwise you must ensure that every device that can drive the CPLD is singing a compatible tune.

For example, why doesn't a resistor pull a 3.3V CMOS device's output up to 5V? Because the CMOS output includes ESD protection diodes which effectively haul the output down to one Schottky diode drop above VCC, so about 3.6V. The resistor trick only works for TTL outputs, as found in 74LS devices.

The correct way to connect a 3.3V CMOS output to a 5V CMOS input is via a 74HCT or 74ACT or 74AHCT buffer. That's because the T-series inputs are TTL level compatible, and 3.3V CMOS outputs actually meet that spec.

Looking at the datasheets from the W65C21S and the W65C816S. I wonder how they would actually work together - they are not compatible Voltage-wise if I read it correctly...:

1. The Input High Voltage Vih on the W65C816S for e.g. the data bus is min VDD x 0.8, i.e. 4V for a 5V supply. Voh on the '816 isn't even documented at all.
2. The Output High Voltage Voh on the W65C21S for the data bus is 2.4V min. Vih is 2.0V

So, if the '21 just delivers 2.4V on the data bus, the '816 would not reliably read it.

Similarly the difference between the W65C22S and W65C22N - here both specs are even on the same page.
1. Voh on the "N" is 2.4V. Vih is 2.0
2. Voh on the "S" is not documented. Vih is VDD x 0.8.


Hm. Not sure what to make of it. My guess is, that the Vih on the '816 is wrongly documented, what do you think? What would it be really?

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/