What the MCS6500 Microcomputer Family Hardware Manual actually says is:


In other words, as I read it, you can bring READY low any time you like, but if you do this during a write cycle, the CPU will still continue to execte cycles until the next read cycle. Woz's single-step circuit does essentially the same thing as the MOS single-step circuit, just in a much less complex way and with a lot less extra debouncing circuitry, so there should be no issues there.

(I know that this thread is old, but I am guessing that some people may still come across it and use it for reference. The loss of the OP's original schematic is a demonstration of why it's a good idea to attach such things here rather than referring to an external source.)

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Curt J. Sampson - github.com/0cjs

Hmm, both the original and the suggested alternative based on a 74LS76A have gone AWOL. Maybe they're still in archive.org, I haven't checked.

Woz' version using a 7474 is interesting, but depends on the TTL input which effectively includes a soft pull-up. It would need a redesign to work with modern CMOS logic, at minimum adding pull-up resistors in some places. Maybe I can figure something out.

It's reasonably well-known that the NMOS 6502 doesn't wait on /RDY for write cycles; the VIC-II in the C64 drives RDY low 3 cycles before it needs any Phi2 cycles precisely to accommodate the longest possible sequence of consecutive write cycles, and this is something that demoscene authors regularly have to pay attention to. The CMOS versions of the 6502 and 65816 *do* halt on /RDY even for write cycles (though you also have to be careful with the bank address latching on the latter). The 65802 is the exception that proves the rule, deliberately aping the NMOS behaviour, almost certainly for Apple II compatibility.

Not halting on write cycles doesn't matter for single instruction stepping. The SYNC cycle is always a read cycle, fetching the opcode byte.

After careful analysis, it appears that the Woz circuit will halt on the second cycle of each instruction in instruction-stepping mode, rather than the opcode-fetch cycle that most people would expect. That's simply because it clocks the right-hand flop with Phi1, whose rising edge is at the very end of the cycle in which SYNC rises. If it were clocked with Phi2, then this would be fixed, and I don't think it would impair single-cycle operation either.

I was able to rebuild this circuit around a 74HC(T)109 JK flipflop by adding just two pull-up resistors, which are overridden only briefly (one cycle or one instruction) for each Step button press and release. All other necessary pull-ups and pull-downs are hard shorts to the power rail and are never overridden. The '109 is a little special in that the K inputs are active-low, so it can be used as a D flipflop by tying J and /K together, at which point it behaves just like a '74. It's also available in the 74AC family for higher-speed applications.

My initial attempt to modify the circuit to cope with the 65C02's single-cycle NOPs (which may hold SYNC high continuously), however, is incompatible with the change in clocking described above. I was thinking to feed SYNC to the J input of the left flipflop and use Phi2 as its clock. This would however return to the problem of halting on the second cycle of an instruction, regardless of how the right-hand flop is clocked. This would be less of a problem if a quadrature clock were available, as then the right-hand flop could be clocked halfway through Phi2, or the left-hand one could be clocked halfway through Phi1.

It might be possible to work around this by adding an AND gate chip, the spare gates of which would also be useful for solving related problems surrounding this circuit in some systems.

This is great work, Chromatix! What are the sort of "surrounding problems" you're talking about?

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Curt J. Sampson - github.com/0cjs

Things like combining RDY sources from wait-state generators with that of the stepper, and generating SYNC from the '816's VDA and VPA signals.

For the time being, here is the direct translation of Woz' design to the CMOS age, plus the switch to Phi2 clocking. This version should work with both CMOS and NMOS 6502s, with the caveat that single-cycle NOPs on CMOS CPUs will be treated as "prefixes" to the first subsequent real instruction in instruction-stepping mode, and of course NMOS CPUs will not halt on write cycles in single-cycle mode. The 74HCT part permits use with NMOS CPUs, but can be substituted with a 74HC or 74AC equivalent for optimum CMOS operation.



Broadly speaking, it works like the escapement mechanism of a mechanical clock. The whole thing is bypassed, with RDY held permanently high, when the Run/Halt switch is set to Run (tying the right /S pin to GND). The SPDT pushbutton switch greatly simplifies debouncing by positively registering both pressed and released states, unlike the SPST switches commonly found in keyboards. Locating such a switch is left as an exercise for the reader.

In the released state, it holds the left flop in the cleared state, and that is the only way that this flop can be cleared. But only when the button is pressed is this state used to trip the right flop into the set state, which raises RDY for the next Phi2 phase. The CPU samples RDY on the Phi2 falling edge, so having it stable at that moment is probably the correct design.

The right flop is automatically cleared (lowering RDY) when either the pushbutton is released or the left flop is set; the latter occurs either on a rising edge of SYNC (which occurs during the Phi1 phase of an opcode fetch cycle, as SYNC is in the "address" group of signals for timing purposes) or immediately after the right flop is set if the Instruction/Cycle switch is set to Cycle (tying the left /S pin to the right /Q). Both of these are in good time to clear the right flop on the next Phi2 rising edge.

Note that in normal operation, the two signals that are pulled by resistors are actively driven to that state at the end of their override period, so the resistor only needs to hold the line in that state and its value is not timing-critical. With CMOS inputs being extremely high impedance, power consumption is also negligible.