It’s too close for comfort!Listed above are all the signal paths through the CPU with estimated propagation delays. Highlighted are paths that will require critical routing. Those are paths that will allow less than 3” of cumulative signal trace length (assuming 0.5ns of clock skew and 6” per nanosecond propagation delay through an FR4 pcb). It’s going to be a neat trick to route these critical circuits within the prescribed maximum trace lengths. The tolerances here are making my head spin!

For reference, the following logic families are assumed:

• AVC (3.3V) — Registers
• NC7SV (3.3V) — Gates and flip-flops
• LVC (3.3V) — Decoders and counters
• CBTLV (3.3V) — Muxes
• AUC (2.5V) — 74AUC2G53 2:1 switch

The obvious issue is the inclusion of 74AUC2G53 2.5V ICs in this mix. Were it not for them, we could get by solely with a 3.3V supply. But they are essential. So we are definitely into a dual-supply scenario here.

Another possibility is to simply run all parts at say 3V, which is below the Absolute Maximum rating of AUC parts and only slightly below the Recommended VCC of the 3.3V families. I’m not sure what kind of safety margin is needed to keep those ICs happy. Certainly I was able to run the AUC FET Adder at 3.3V without frying any chips! Maybe a single 3V supply may work?

An alternative mix of families is:

• AUC (2.5V) — Registers
• AUC (2.5V) — Gates and flip-flops
• LVC (3.3V) — Decoders and counters
• CBTLV (3.3V) — Muxes
• AUC (2.5V) — 74AUC2G53 2:1 switch

This mix of parts has slightly longer average tpd figures and slightly lower output drive but also lower input pin capacitance associated with AUC parts. AUC also features variable impedance outputs whereas NC7SV gates don’t. The former are far better for transmission lines, but in many situations gate-level ICs are used only within lumped circuits in any case. Honestly, I’m not at all sure which mix of parts if going to best at this stage. We may have to wait until the layout before the better alternative is clear.

In the meantime, I would very much appreciate any thoughts anyone might offer regarding the relative safety of running ICs a little hot, but below their rated absolute maximums. Is that pushing luck too far?

Cheers for now,
Drass

_________________
C74-6502 Website: https://c74project.com

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Most parts will suffer a loss in speed when run below their nominal voltage.

I vote for the alternative mix, and for having 2.5V and 3.3V polygons on one PCB layer if possible.
To me, mixing 3 different logic families in the same design somehow feels safer than mixing 5 different logic families in the same design.

We need to take a closer look at the signal paths with a propagation delay slower than 8.9ns.
Capacitance is going to be a critical factor, we need to take a closer look at it, too.
At 100MHz, address decoding is an interesting (and still open) topic.

Would suggest to draw one big schematic for the whole CPU first while placing the chips in a *.brd file
by sorting/grouping the chips according to functional groups in the CPU block diagram,
just for getting a rough overview about how many chips we have in total, and how they are "wired" together,
and if\how\where we would be going to need line termination of the control (and\or data) signal traces.

This (hopefully) will tell us, how to break the big schematic into a set of smaller schematics
for the set of PCBs the CPU will be made of while trying to keep the PCB traces as short as possible.

Drass, it would be helpful if you could post a more detailed block diagram of the CPU.

I'm reminded of the discipline of the Cray-1 implementation: an 80MHz machine
"The 12.5 ns clock is divided into eight “gate times” of about 1.5 ns each. Roughly half the gate time is due to circuit propagation delay, and half is due to board-foil delay."
Two papers for those interested posted over here on anycpu.

Ed, thanks for the link.
The interesting part:

"Designing the Circuits CRAY-1 modules are 6 inches wide.
The distance across the board is about a nanosecond which is just about the edge time of the electrical signals.
Unless due precautions are taken, when electric signals run around a board, standing waves can be induced in the ground plane.
Part of the solution is to make all signal paths in the machine the same length.
This is done by padding out paths with foil runs and integrated circuit packages.
All told, between 10 and 20 per cent of the IC packages in the machine are there simply to pad out a signal line.
The other part of the solution was to use only simple gates and make sure that both sides of every gate are always terminated.
This means that there is no dynamic component presented to the power supply.
This is the principal reason why simple gates are used in the CRAY-1.
If a more complex integrated circuit package is used, it is impossible to terminate both sides of every gate.
So all of the CRAY-I's circuits are perfectly balanced.
Five layer boards have one ground layer, two voltage layers, and then the two logic layers on the outside.
Twisted pairs which inter- connect the modules are balanced and there are equal and opposite signals on both sides of the pairs.
The final result is that there is just a purely resistive load to the power supply!"

BTW: 6 inches would be 152.4 mm.

Hmm... it's an interesting question whether to use standard FR4 PCB material, or special high frequency PCB material.

Bil Herd has some interesting info on high speed PCB design as well: https://hackaday.com/2019/01/24/video-p ... -the-test/

Arlet, also thanks for the link.


TI application report SCEA027A from 2002, 74AUC, the pictures on PDF page 18.
Considering something like a 500ps rise time, the maximum frequency "hidden" in the rising edge of the signals would be 700MHz+.
//Starting to think that we probably could get away with FR4, but I would suggest to get a second opinion on this.


I wasn't aware of _that_ effect.
Drass: once we have a PCB layout, maybe it would be a good idea that you nicely/politely ask Bil Herd if he could take a look at it...

Project abandoned by ttlworks due to 2014/40/EU.
Not my decision. Sorry that. Good luck.

Wow. I didn't know PCBs were made from tobacco.

Hi Drass,

I'm unsure if you have already mentioned this in the past, but I am curious about what are you using for your instruction decoder. It looks to me that the typical ROMs are totally out of specs for your speed requirements, so what are you using instead?

(It would also be great if at some time you eventually post a CPU diagram showing the modules you listed for your critical path calculations)

If I understand it well, it looks that the Klaus Dormann suite makes use of self modifying code for some tests. At some time in computer history, self modifying code was deprecated, maybe after processors incorporated security features, or memory caches, or to avoid trouble in the pipeline.

I'm intrigued about self modifying code in relation to your cpu implementation, because I suppose that it is only problematic if it happens to an instruction that is already in the pipeline, which should be relatively rare in real life code. So maybe it can generally be ignored (?). How this subject fits in your pipelined processor?, are you supporting this in some way?

Thanks!

Yes, that’s the plan. The stackup is not quite fully worked out, but for sure there will be components on both the top and bottom layers. The current thought is to go with a 6 layers, as follows:

Signal Top
— 5 mil prepreg —
GND
— 5 mil core —
Signal V
— ~40 mil prepreg —
Signal H
— 5 mil core —
VCC
— 5 mil prepreg —
Signal Bottom

This would be on a 1.6mm FR4 (7628) PCB, with 8 mil microstrip and 6.5mil stripline traces to yield 50Ω impedances. If the VCC plane becomes too fragmented due to the dual-voltage supply requirement, then it might be necessary to either turn Signal H into a VCC2 plane or go to an 8 layers board. Dr Jefyll has done some great work to confirm the use of VCC as a reference plane in various scenarios, which is great. I will need continued help to finalize the stackup when the time comes (which I suspect will be partially into the layout).

IIRC, a blind via perforates the PCB from one surface to the required layers and no further, whereas a buried via does so only from one specific internal layer to another without harming the PCB surfaces at all (hence buried within the PCB). My current plan is to use regular through-hole vias, but I can certainly see how these other variants might become necessary.

I have a bias towards simple drag soldering, rather than paste and stencils, simply because of familiarity. I’m definitely open to suggestions though so I might come back to this topic when the time comes. One question: is it practical to use solder paste and stencils when there are components on both the top and bottom layers? How do you keep the bottom components from falling off or shifting when heating the boards?

Yes, thanks for mentioning it. It may come very handy in this project. (I think Arlet may have made the same suggestion for the C74-6502 but I was too much of a noob to venture it).

_________________
C74-6502 Website: https://c74project.com

No problem. I do that all the time. The components on the bottom will just hang by cohesion forces. Only real heavy stuff like chunky inductors sometimes fall off. It helps if your oven has more top heating than bottom heating.

If you're going to use blind/buried vias, keep in mind that not all PCB manufacturers have that capability. Those that have may charge a much higher price, and also have restrictions on what you can do. So, before you use them, pick a manufacturer, check the cost, and get their design rules before finishing the entire layout.

Yes, I agree. I was thinking about it as a compromise where 2.5V parts run faster than spec and 3.3V parts slower, but it more or less averages out. The main question is whether I can get away with a single supply. I tested 2.5V 74AUC2G53s at 3.3V and all was fine ... their Absolute Maximum rating is 3.6V. I’m wondering whether planning on a single supply that can be pushed up to 3.3V if necessary is reasonable. (i.e. to run the 2.5V parts well above the “recommended” range but still below the “maximum” range). I don’t fully understand the safety margins required so this may be a crazy idea that should be quickly abandoned.

_________________
C74-6502 Website: https://c74project.com

Maybe insert a small diode between the 3.3V net and 2.5V pin ?