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 Post subject: SOJ-to-DIP SRAM Adapter
PostPosted: Mon Nov 16, 2020 11:59 am 
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Joined: Sun Jun 29, 2014 5:42 am
Posts: 352
Hi all,

I'm posting this in a seperate thread as it might be of wider interest.

As part of Beeb816, we use a 55ns 5V 512Kx8 SRAM in in DIP 32 package. We wanted to try out a faster 10ns part, but these are only available in surface mount (SOJ and TSOPP) packages. Before respinning the whole board, we though we would try an adapter shim.

The design files are in github:
https://github.com/hoglet67/SRAMAdapter ... ster/kicad

There is a two layer version:
Attachment:
ram_adapter_2layer.png
ram_adapter_2layer.png [ 40.84 KiB | Viewed 899 times ]

And a four layer version:
Attachment:
ram_adapter_4layer.png
ram_adapter_4layer.png [ 38.58 KiB | Viewed 899 times ]

The SRAM is in an SOJ-36 package, which just fits between the DIP pins:
Attachment:
ram_adapter_4layer_3d1.png
ram_adapter_4layer_3d1.png [ 95 KiB | Viewed 899 times ]

The decoupling capacitors are hidden underneath:
Attachment:
ram_adapter_4layer_3d2.png
ram_adapter_4layer_3d2.png [ 50.09 KiB | Viewed 899 times ]

We ended up going with the 4-layer verstion, which cost just $5.00 for 10 boards from JLCPCB.

This is the first board off the production line, fitted with an a 10ns ISSI IS61C5128AL-10KLI part:
Attachment:
IMG_2118.JPG
IMG_2118.JPG [ 340.1 KiB | Viewed 899 times ]

And fitted in Beeb816:
Attachment:
IMG_2131.JPG
IMG_2131.JPG [ 483.96 KiB | Viewed 899 times ]

With this, Beeb816 runs stably at 20MHz (previously the limit was about 14MHz):
Attachment:
capture0.png
capture0.png [ 2.23 KiB | Viewed 899 times ]

I've built three of these, for the three prototype Beeb816 boards.
Attachment:
IMG_2122.JPG
IMG_2122.JPG [ 477.31 KiB | Viewed 899 times ]


Feel free to make use of this work if you have need for such a thing.

Dave


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PostPosted: Mon Nov 16, 2020 12:17 pm 
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Well done Dave - very nice repackaging and a fine result!

I think it turns out that the usual 55ns parts are barely able to support 14MHz, so moving to 10ns is a great leap forward! And we keep the DIP format, the green PCB with lots of drilled holes, if we choose to.


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PostPosted: Mon Nov 16, 2020 2:06 pm 
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BigEd wrote:
I think it turns out that the usual 55ns parts are barely able to support 14MHz

Only just, yes, depending on their internal organisation and address decoding (since access time basically starts at address stable, not the strobe).

ReCo6502 ran at 14.7 MHz with 55 ns DIP SRAM. With the same construction you have here (SMD on DIP header) a 25 ns SRAM brought that to 22 MHz. I think others have reported even higher numbers than that. The headroom of 14 MHz WDC chips is astonishing, almost up to the point of having to conclude gross underspecification ...


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PostPosted: Mon Nov 16, 2020 3:35 pm 
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Interesting datapoint, thanks!


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PostPosted: Mon Nov 16, 2020 5:25 pm 
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Windfall wrote:
The headroom of 14 MHz WDC chips is astonishing, almost up to the point of having to conclude gross underspecification ...

That's because production testing is done at 20 MHz.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


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PostPosted: Mon Nov 16, 2020 6:41 pm 
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BigDumbDinosaur wrote:
Windfall wrote:
The headroom of 14 MHz WDC chips is astonishing, almost up to the point of having to conclude gross underspecification ...

That's because production testing is done at 20 MHz.

If only Intel did that. I could safely run my i9-7920x at 6.14 GHz ...


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