Go, Drass, go.

;---

Not relevant for this project:

While flipping through the pages of the TI Digital Logic Pocket Data Book 2007, I noticed an interesting chip:


TI 74LVC1G0832
3.3V, 15pF load: 1.7 / 3.35? / 5
5V, 15pF load: 1.2 / 2.3? / 3.4

Nexperia 74AUP1G0832
3.3V, 15pF load: 1.9 / 3.2 / 4.5

These chips are too slow to be used in our 100MHz CPU.
There is no 74AUC version of that chip in production... yet.
But an AND gate feeding an OR gate, that's the ALU carry chain for one Bit.

74LVC1G3208 and 74AUP1G3208 also are available, an OR gate feeding an AND gate.

Cute, now back to 74AUC2G53...

I found these chips some time ago and also thought they were interesting (for projects at 74ACxx speeds, at least).

They appear under the "Logic->Configurable-Gate" section on the Texas Instrument site https://www.ti.com/logic-circuit/gate/configurable-gate/products.html along with other interesting ones.

Regarding decimal mode, I took a closer look at how the 100181 4 Bit ECL ALU does decimal arithmetic.

To me the concept looked interesting, because the carry chain doesn't need to be broken into nibbles, and because the decimal correction at the ALU output looks more simple.
//It can't generate the correct incorrect flag results for the NMOS 6502, of course.


Unfortunately, we can't use the 100181 decimal mode concept in our project:

For decimal SBC, I think it would be compatible to a 65816 (not to a 65C02) for decimal and non_decimal numbers at the inputs.
For decimal ADC, unfortunately it only would be 65816\65C02 compatible for decimal numbers at the inputs, but not for non_decimal numbers at the inputs.

It was worth a try.

;---

Edit:
The 74F582 was a decimal adder\subtractor.
It's not relevant to this project, because the chip is out of production, it's not available, it's too slow, and the circuitry won't bring us far.
74F582 seems to be a ripoff of the Signetics 82S82.

TI 74F582.
Fairchild 74F582, PDF page 514.
Signetics 82S82, PDF page 589.

One would expect that companies like TI and Fairchild are able to draw schematics... but a few connections in their schematics are missing.
Also, Fairchild "forgot" inverting an input at two NAND gates.
Looks like the Signetics 82S82\82S83 schematics have errors, too.

Baked up a simulation from parts of the Signetics 82S82\82S83, TI 74F582 and 74F583, and Fairchild 74F582 schematics.
From the simulation results, the 9s complementer at the left of the 74582 schematics can't handle non_decimal numbers.
//the 74583 decimal adder is a subset of the 74582.
//74583 carry chain does work for non_decimal numbers at the adder inputs, but the 4 Bit data output only gives valid results for decimal numbers at the adder inputs.

74582 BCD adder\subtractor simulation:

Thanks for giving that a try Dieter. I took a look at an approach for Decimal Mode, described below.

The basic method for Decimal Mode is to perform an ADD or SUB operation, and then convert the result to BCD. The process is to work on each nibble in turn, as follows:

Adder LO --> Detect LO --> Generate LO --> Adjust LO --> BCD result LO
Adder HI --> Detect HI --> Generate LO --> Adjust HI --> BCD Result HI

Detect_LO tests to see if the lower nibble needs to be adjusted. This would be the case if the the binary result is greater than 9, or if the low-nibble carry (C4) is high. To adjust an ADD result, Generate_LO will generate a 6 (or 0 if no adjustment is needed) which is then applied to the binary result by Adjust_LO. Generate_LO will also generate a BCD low-nibble carry (BCDLC) in that case. The process is the same for the upper nibble, except that BCDLC must be added to the upper nibble result. The same logic holds for subtraction, except that Generate_LO and HI will produce a $A rather than a 6 to perform the adjustment.

Now the binary adder alone consumes the entire cycle at 100MHz, so Decimal Mode at high speed will need to take two cycles to complete (like it does on the 65C02). A happy consequence of this is that we can use the ALU adder for both the original binary operation and the subsequent adjust operation. To do so we feed the result of the initial binary addition back into the ALUA input, and feed an appropriate Adjust Value into the ALUB input for each nibble.

Because the binary result for the lower nibble emerges from the adder early in the initial cycle, we are able to generate the lower nibble Adjust Value in the same cycle, like this:

Cycle 1: Adder LO --> Detect LO --> Genereate LO --> ALUB
Cycle 2: ALUB LO --> Adder LO (B input) --> BCD Result

The high nibble, on the other hand, is not ready until the very end of the initial cycle. We must therefore generate the Adjust Value for the high nibble in the second cycle, like this:

Cycle 1: Adder --> ALUA
Cycle 2: ALUA HI --> Detect HI --> Generate HI --> Adder HI (B input) --> BCD Result

This will work, as long as the high nibble Adjust Value can be generated quickly. Adding an alternate path to the B input of the adder will add capacitance, but only minimally so and only to the high order bits of the carry-chain where we can tolerate some delay.

Thanks to Dr Jefyll and ttlworks, the BCD adjust circuit in the C74-6502 is very fast already, and we can adapt it for our purposes here. This circuit produces results that are compatible with the NMOS 6502 for both decimal and non-decimal inputs. It uses FET Switches for time critical logic. With a little rejigging, we can adapt it to work in this new design, as is shown in this rough schematic:
The high-nibble Adjust Value is generated by four FET Muxes in series (BCD.DETECT.HI, BCD.DETHI.AUX, BCD.SEL.HI and ALUB.SEL). This value is then fed into the high-nibble of the FET Adder. Earlier tests showed that CBTLV switches took about 1ns longer than AUC parts in the carry chain. The Adjust Value path is therefore likely to delay the adder result by that margin as well. Thankfully, because the results of Decimal Mode operations are never used as addresses, the Adjust Value path does not have to meet the 1.5ns setup time of the synch RAM. We therefore should have just enough extra time for this path to work.

In order to remove from the adder the delay associated with the BCD carry, it’s easiest to break the carry chain at C4 and perform to separate adds for the low and high nibbles. The BCD carry can then be added in at the end as bit 0 of the high-nibble Adjust Value. In order to make this work, Detect_HI must adjust the threshold to test for > 8 for addition and < $F for subtraction. The ADJ1 and ADJ7 values that are input to BCD.DETECT.HI achieve that in the schematic above.

We can separate the FET carry chain at C4 without adding capacitance by using the INH pin on the 74AUC2G53 C4 IC. An alternate C4' tied to GND can push a zero into the carry chain as needed. Both C4 and C4' can be switched before the ripple carry arrives if the control signal is generated early in the cycle. A 75AUC1G74 that is pre-loaded in the cycle ahead of the ALU operation can generate active-low and active-high control signals to make the switch. (The BRK.CARRY signal going to the FET Adder in the schematic illustrates that function).

One final note regarding flag evaluation: we can use the final BCD adjusted result to obtain the correect results for the N, Z and V flags. This behaviour is compatible with 65C02 and the 65816 CPUs. The NMOS 6502, on the other hand, calculates the flags based on the original binary sum, but with the BCD low-nibble carry (BCDLC) added in. Since this value is no longer calculated by the ALU adder, we can include a simple 4-bit incrementer to add BCDLC to the upper nibble of the binary sum. This would be done during the second cycle of the BCD operation.

As will likely be the case with everything in this design, we meet the required timing for this circuit only by the skin of our teeth. It will be impossible to know whether we will reach the target clock-rate until the whole CPU is built. For now, I am doing my best to account for even the smallest delays, and have taken to including clock-skew and trace propagation delay in my estimates of the critical path. That will give me some idea of which components will need to be near each other in the final layout. At these speeds, just getting signals from one side of the board to the other is going to be a challenge!

Cheers for now,
Drass

_________________
C74-6502 Website: https://c74project.com

Wait, hold the phone!

The carry chain is in fact split at C4 for the initial binary add as well. That means that the low and nigh nibbles emerge from the adder at exactly the same time, early in the cycle! So we can in fact make a start on the high-nibble Adjust Value in the initial cycle as well, and ease the time crunch on the second cycle. We only really have to capture the BCDHC and /BCDHC and we can generate the Adjust Value in the second cycle from that. Nice.

Phew! Feels good to come across a couple of unclaimed nanoseconds — it’s like finding an open parking spot downtown.

_________________
C74-6502 Website: https://c74project.com

Drass, that's impressive work.

Haven't checked your schematic in detail, but now some suggestions:

Using two 74AC541 chips (ROUT.ALUA and ADJ.ALUB) for injecting data into ALUA.BUS and ALUB.BUS would increase the bus capacitance there,
and it adds to the propagation delays.

ADJUST.LO happens to be a 74AC574 with output enable, so to me it would make sense to wire the ADJUST.LO outputs directly to the
outputs of the ALU.B register (which also is a 74AC574), then to make creative use of the output enables of both chips.
;
Also, I would replace the ROUT.ALUA (74AC541) with a 74AC574 with outputs wired to the outputs of the ALUA register (74AC574)
and to make creative use of the output enables of both chips.

Hmm... ALUB.SEL (74CBT3245) select input is switched by a signal generated by the BCD2.A flipflop.
In theory, you could replace ADJUST.LO (74AC574) by two 74AC574 chips, one feeding ALUB7..4, the other feeding ALUB3..0,
and to do some more creative tinkering with the output enables.
This would throw the ALUB.SEL chip out of the design.

WB (74AC574) has some spare flipflops, so it looks ideal for throwing flipflops like ALUC.A and BCD2.A out of the design,
but this sure won't increase the readability of the schematics.

(Is there a simulation setup being used for these ideas, or is it all by brain power alone? If it were me, I'd quite like to run an exhaustive 512 calculations...)

Thanks Dieter. Coming from you that means a lot.

Agreed. These would likely be FET switches in the final design but capacitance is nevertheless going to be an issue. There are several buses with significant load on them, and ALUA and ALUB are among them. Also, with many ICs on those busses, trace length and termination will be issues as well. No shortage of things to worry about.

Nice! I think it works Dieter. Great suggestion.

This does, however, bring up a good point worth discussing. CLK-to-Q tpd and Output-Enable-time are usually pretty close (they are on 74AUC16374s, for example), but there is additional delay required to generate an OE control signal. In general, an OE signal is only likely to arrive at a register after a CLK-to-Q delay (assuming no decoding) of wherever that control signal is coming from.

The BCD2 flip-flop and ALUB in the schematic above make for a good example to illustrate the point. Say we used BCD2 to generate BCD.CYCLE2 and /BCD.CYCLE2 control signals to output-enable ALUB and ADJUST.LO respectively (as I think you are suggesting). That makes sense. We get ALUB normally, and then switch to ADJUST.LO for the BCD2 cycle. That's good, but now the data from ALUB arrives at the FET adder after the CLK-to-Q delay of BCD2 PLUS the OE time of ADJUST.LO. By contrast, the data from ALUA arrives at the FET adder after just a single CLK-to-Q delay.

The additional OE delay for ADJUST.LO is fine in this case because we split the FET carry chain in to 4-bit segments for BCD operations. But it would not be ok for an 8-bit binary operation which might follow when switching back to ALUB. We are saved in this case by the fact that the cycle after a BCD operation never requires the ALU, so we get a free cycle for ALUB to switch back. In other situations, however, the switching delay would be prohibitive.

ROUT.ALUA is used during normal 8-bit binary operations so unfortunately I don't think we can afford the switching delay in this case.

Yup, this works nicely, along the lines described above.

In the final schematic we might have to sacrifice readability for PCB real estate. I think you're right to point it out.

Some great suggestions here Dieter. I'll make a note of the improvements for the next rev of the schematic. Thank you!

Of course your'e right, BigEd. Thanks for the comment.

The Logisim model for this design is still a work-in-progress. I do have this specific BCD circuit modelled and have manually run the inputs through a range of values to confirm the results. But it's by no means exhaustive. That will have to wait. In the meantime, I am comforted by the fact that the basic logic is the same as in the C74-6502, which has been tested exhaustively. With some luck, I won't find major errors in this rendition of the circuit when I finally do get the model up and running.

_________________
C74-6502 Website: https://c74project.com

Here his V2 of the Decimal mode circuit incorporating the changes as discussed. It looks much nicer. This version moves part of the BCD.ADJUST.HI processing to the first cycle (namely BCD.DETECT.HI), and uses the BCD2 flip-flop to Output-Enable ALUB and ADJUST for the first and second cycles of the BCD operation respectively. I was also able to eliminate the WB register entirely by using ADJUST to hold all inter-cycle info.

Notes:

• BRK.CARRY: needs to come directly from a flip-flop to split the carry chain (i.e. no decoding of microcode, otherwise the high-nibble of the adder will be delayed). It should remain set for both BCD cycles.
• ROUT.ALUA indicates that the ALU output (Rout) is fed back into the ALUA register. This "recirculate" path is used for other functions as well. The control signal is driven by the microcode. It can be decoded in-cycle.
• BCD.CYCLE2 also is driven by the microcode. It should be asserted during the first cycle of a Decimal Mode operation. It can be decoded.
• ADC and SBC come from decoding the opcode and are available throughout both cycles.
• FET Nibble Adder: a 4-bit carry chain is used for each the high and low nibbles of the FET Adder independently. The tpd of a 4-bit FET adder is 3.5ns conservatively.
• C4, C8: are the low and high nibble carries respectively. C4 will tap the FET carry chain and will therefore add a bit of capacitance to the binary 8-bit carry chain (3pF). The additional delay should be minimal.
• ALUB: BCD2 CLK to Q and ALUB OE will impose a delay when switching back to ALUB after the second cycle. This is ok because the ALU is always idle in the cycle that follows a Decimal mode Operation.
• 1st cycle tpd:
  ALUA, 74AUC16374, CLK to Q = 1.5ns
  FET Adder, Nibble tpd = 3.5ns
  BCD.DETECT.LO, 74CBTLV3251, Sel to Y = 2.8ns
  BCD.SEL.LO, 74CBTLV3257 Data to Y = 0.25ns
  ADJUST, 74AUC16374 setup time = 0.6
  Clock-Skew = 0.5ns
  3" trace @ 50Ω= 0.5ns
  Total = 9.65ns
• 2nd Cycle tpd:
  BCD2, 74AUC1G74 CLK to Q - 0.8ns
  ADJUST, 74AUC16374 OE = 1.5ns
  BCD.DET.HI.AUX, 74CBTLV3253 Sel to Y = 2ns
  BCD.SEL.HI, 74CBTLV3257 Data to Y = 0.25ns
  FET Adder, Nibble red = 3.5ns
  RESULT, 74AUC16374 Setup = 0.6ns
  Clock-Skew = 0.5ns
  3" trace @ 50Ω = 0.5ns
  Total = 9.65ns

Both paths are nicely balanced.

Alright, this feels like we're in a good place for now. Thanks for the comments and feedback!

Cheers,
Drass

_________________
C74-6502 Website: https://c74project.com

Hi Drass, It gets confusing that you use different ic references in the schematic and the description, (some do not even match in pin layout or function, but I assume that particular one must be a typo). In at least one case you exchanged analog switch type circuits, where disabled outputs become high impedance, by chips with low disabled outputs, which act very differently. You also refer to 16 bit versions of registers in the description, but there's only 8 bits on the schematic. Please, can you comment on this?

Apologies Joan. It looks like I included my back-of-the-napkin tpd in that post rather too hastily. There is a lot of shorthand there!

Let me explain:

This schematic is more of a sketch as to how we might solve the problem, rather than a fully worked out spec. We have not decided yet which IC families to use for which compoenets, as there are tradeoffs to consider for each situation. For example, 74AVC16374 registers are faster than 74AUC16374s, but they also impose more capacitance on their inputs — not to mention the supply voltage differences. We might choose one or the other in the final design, or even use each for different aspects of the design. In the meantime, I just used AC chips as place holders. For example, I used 74AC574s as registers where in fact a pair of these might be implemented with a single 74AUC16374 in the final design. I used the 74AUC16374 figures for the back-of-the-napkin tpd because it’s the slower of the two alternatives we are considering.

Regarding the 74AC151, yes, it’s a powerhouse of an IC. Sadly, it’s not available in any of the logic families we are considering. I’ve yet to find a good replacement, so I went ahead and used the figures from a 74CBTLV3251 since the switch-time is what counts for the critical path. I’m working on the assumption that we will either find a good replacement IC for the final design, or that we might have to go with a “not so good” replacement otherwise.

This not-so-good replacement might require additional ICs, but can be functionally equivalent. For example, the inverted output of the ‘151 might have to be implemented with a 74AUC1G04. Or (if the additional delay associated with the inverter is unacceptable) we might go with two 74CBTLV3251s, and have one with the data inputs inverted. You are also right to point out that the enable input (/G) works differently on a 74AC151 than it does on a 74CBTLV3251. They are equivalent when the /G input is driven low, but when driven high, the CBTLV tristates its outputs, whereas a 74AC151 takes its inverted output high and its non-inverted output low. This behaviour can be emulated with a pair of 74AUC126s and in inverter.

The not-so-good equivalent circuit would then look something like this:(Not sure why the image below is not displaying as a thumbnail as usual )It’s not great, but the critical path is still the Sel-to-Y tpd of the 74CBTLV3251. I simply omitted all this detail in my back-of-the-napkin tpd.

Cheers,
Drass

P.S. Thanks for catching the typo. Yes, that’s supposed to be a 74CBTLV3257. I fixed it now.
P.P.S If someone has any ideas about how best to replace a 74AC151 using AUC, AVC, LVC, or CBTLV logic ICs I would be very appreciative!

_________________
C74-6502 Website: https://c74project.com

Hi Drass,

Thanks for the clarification.

Your replacement of the 74AC151 by 74CBT3251 is interesting. I think that you should be able to replace the inputs of the 74AUC126s by just connections to +Vcc and GND. That would reduce some capacitance on the C1 line, and would also remove the inverter gate on one of them.

Good thought Joan. Thanks for mentioning it. All suggestions welcome!

_________________
C74-6502 Website: https://c74project.com

Did a search, but faster 8:1 multiplexers (with a true push_pull output) than the 74AC151 are not available.

Another option would be to make creative use of 74AUC2G53 SPDT FET switches:

Maybe not relevant for this project:

Die Devices sells bare chip dies, 74AUC2G53 is on their list.
Würth Elektronik is able to bond bare chip dies to PCBs.