Hi guys

A while ago I decided to move from DIP to PLCC for CPU, VIA and logic. I did my best at the time to route the buses but found it difficult at best with some very poor results.
I've decided to revist this and was wondering what people think of having a central address & data bus and then drop lines from the ICs to the bus? My main concern is the bus line lengths as this will obviously extend them.

Here's an example of the one I've just started:



If the above isn't a good approach can anyone suggest a better one?

Don't worry about wire lengths. At these speeds, a few extra inches is insignificant, and a whole circuit board up to a foot across can be considered a "lumped element". Remember, at 100MHz a resonant dipole antenna is 3 metres long, and that gets proportionately longer as the speed gets slower.

I have not attempted to route a PCB based on QFP or PLCC-socket versions of these chips. I think it should be possible to do a decent job, assuming a 4-layer board. However, a branch off a well-defined bus is a valid technique, though it will definitely increase your via count.

I don't know that my layout method is "better" but it is stable at 20 MHz, with the 65C818 in PLCC and discrete logic in DIP. This is on a four-layer board.



As Chromatix notes, we are not running our stuff fast enough to give rise to transmission line effects. Where you need to be most cautious in your layout is in power and ground distribution. A four-layer board makes it easier to route your unit because you don't have to worry about sandwiching Vcc and ground in between signal traces. As the costs to have four-layer boards have come down quite a bit with the Asian board houses, I'd give that some consideration.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I observe that, on both the DIP and square packages, the address and data lines are in a neat sequential order. The PLCC socket brings them out to two rings of pins, but careful choice of which side of each pin to run traces should allow keeping the traces in that sequential order without additional vias.

The only wrinkle arises when you need to route the address lines to a JEDEC memory device - but that is par for the course.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Although it's true that anything not a sine wave has harmonics as high as bandwidth allows, it's surely not true that any particular number of harmonics are important. What's important are things like monotonicity, overshoot, edge rate: and for the most part, important only for clocks and strobes, not for signals in general.

Outside of audio and RF and modulated data, for the most part we are not transporting waveforms: we are transporting levels (usually) and edges (sometimes). Waveforms are just another way of looking at the physical system.

(I'm not saying any observation is wrong here, I'm saying that not all observations are equally important. There are different ways to look at physical systems.)

Thanks for the advice, guys.

I'll have a think on this and do some mapping of the pins used on each device for the busses. I've noticed that an additional downside of having a bus as I originally described is that it takes much more space. As I'm using Eagle I'm limited to 160mmx100mm.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?