DRC2: a 6502 based single board computer

[ttlworks]

Neither would I:
FBGA165 sure isn't a hobbyist friendly package, the pads are below the chip (between the chip and the PCB).

From the drawings, that's a field of 11*15 pads, pads have 0.5mm diameter, 1.0mm distance from center pad to center pad.

There is a story that hobbyists had soldered something like that in an oven, but at 200€ per chip that's pretty daring.
Trying to solder thin enameled copper wire to 165 pads max. "dead bug style" also would be pretty daring.
On the other hand, getting the chip soldered into the PCB by the PCB manufacturer would feel like cheating.

[LeoN]

0xmarcin wrote:

I myself was thinking about using a dual-port RAM with Ben's design, but these are not only hard to find but also either too small (2K) or too expensive... Good for text, but not so for graphics...

What do You think about it: IDT7028L15PF8, 5V, 64Kx16, 15 ns, TQFP100, price $3.13, shipping cost about ~$10?

[Martin A]

You could use single port ram, and still to VGA with a modest graphical resolution as long as the CPU and video are synchronised. The BBC micro managed 640 x 256 in 2 colours without resorting to dual port ram.

How well the necessary multiplexers would fit into Ben's Design I dont know.

Run your CPU at 1/8 of the VGA clock and you have almost 160ns to read your graphical data for shifting out in the "dead" half of the CPU cycle, which is not a major issue with the common SRAM typically being 55 or 70ns.

I have to confess though I've done ram sharing between a W65C02 and VGA using single port ram, I used a CPLD rather than 74xx logic to do the heavy lifting.

[ttlworks]

Of course it simplifies the design if the CPU is clocked by the CRT controller.

But the point about the D04 CRT\LCD controller is, that it's a passive device snooping the CPU bus for write cycles.
Means: no matter if D04 is present in the system or not, the CPU just works.
Also, D04 doesn't mind changing the CPU clock frequency from 1MHz..3MHz.
...And in theory, it's possible to hook more than one D04 to one CPU.

One could implement that in two CPLDs, but to put it this way:
Some time ago I had some bad experiences with CPLDs which had _brought_ me into TTL tinkering.