While building that 20MHz TTL CPU, we had spent some months with trying to shave off the one or other
nanosecond from the propagation delays in the design.
This was quite a battle, and when building a 100MHz+ CPU we will have another battle of that sort, but in steps of
200 picoseconds or such.
So clock generation/distribution (especially CPU register write clock signals) now becomes a very serious topic,
because any "air gaps" we happen to have in the clock generation/distribution will have dire effects\consequences on the whole design later.
//Stabilizing the leaning tower of Pisa and such.
In our 20MHz TTL CPU, we had used 74AC273 for generating the CPU register write clock signals.
Unfortunately, the 74AC datasheets
don't tell you much (PDF page 13) about the skew between two 74AC outputs.
A
Fairchild appnote from 1988 about FACT (74AC related) says on PDF page 2, that the output skew is 0.5ns typ., 1ns max.
The IDT
high speed CMOS logic design guide 1993 has some info on PDF page 48 (figure 6)
about the "output skew of 74FCT244 versus the number of simultaneously switching outputs, related to the ground bounce problem".
//When generating the CPU register write clock signals, only one output of a 74AC273 is supposed to go HIGH at a time.
Of course we took a closer look at nowadays clock distribution chips, chips with synchronous output enable,
but after an extensive search it became clear that these chips are just designed for enabling/disabling a clock signal (maybe for power saving),
but they certainly are _not_ designed for gating a _single_ clock pulse. //When having CMOS\LVCMOS outputs.
;
Really, when searching for such chips, you _carefully_ need to read the datasheets, checking for:
0) clock frequency at which the chip can operate, 0.985MHz (C64 PAL) < f < 150MHz+
1) three_state or default_low output //default_low good, three_state bad.
2) synchronous or asynchronous output enable //synchronous good, asynchronous bad.
3) propagation delay enable to output //5ns is too slow.
4) clock delay enable to output //next rising/falling edge of the clock signal good, 1..3 clock cycles delay bad.
;
We failed to find a clock distribution chip with CMOS\LVCMOS outputs that meets all of these requirements, from all of the chip manufacturers listed at Mouser.
A good candidate for building the CPU registers would be TI
74AUCH16374 (that's 2*74374 in one package).
In theory, PotatoSemi
PO74G374 looks nice too, but it isn't quite the thing for driving capacitive loads on a bus.
;
Unfortunately, there is no 74AUCH equivalent of the 74377 (register with synchronous load enable),
and there is no 74AUCH equivalent of the 74163 (counter with synchronous load enable),
so when using 74AUCH we can't get around ending up with the equivalent of a 74374 for building the CPU registers.
There is no 74AUCH equivalent of the 74273 (register with RESET input), so we have to spend some more thoughts on how to generate these CPU register write clock signals...
And no, PotatoSemi doesn't have a 74273 equivalent.
Edit:
Registered buffers for DDR2 (like the
SSTUH32864) don't have an output enable,
are very exotic, and it's hard to tell for how long they would stay in production.
We better not use them.
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The additional drive has done it, and we even have a reasonable safety margin. Dieter’s FET Switch Adder as enhanced by Jeff is a winner! 
