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BillG
PostPosted: Wed Sep 23, 2020 6:02 am 
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It seems I spoke too soon. Constant = -2 and S1 = -1 now works.

I'll shut up until this is figured out.
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BillG
PostPosted: Wed Sep 23, 2020 12:10 pm 
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A new morning brings with it an organized approach to analyzing the situation. The code generator was modified to include a test harness. By setting a breakpoint at $41, the result for each value of S1 can be seen. S1 = 7F is where it begins to break down:

Code:
                          00031 ; W0 := -1 - S1;
                          00032
                          00033 ;   ;  0 := v W0 -> 1
                          00034 ;   ;  1 L r 2
                          00035
                          00036 ;      ;  2 L c -1 -> 3
                          00037 ;      ;  3 - v S1
                          00038
                          00039
                          00040 ;  1 L r 2
                          00041 ;  2 L c -1 -> 3
                          00042 ;  3 - v S1
 0029                     00043 99:
 0029 A5 16           [3] 00044          lda    S1        ; A = 7F
 002B 49 7F           [2] 00045          eor    #$7F      ; A = 00
 002D 18              [2] 00046          clc
 002E 69 80           [2] 00047          adc    #<65408   ; A = 80, C=clear
 0030 AA              [2] 00048          tax
 0031 A9 FF           [2] 00049          lda    #>65408   ; A = FF
 0033 69 00           [2] 00050          adc    #0        ; A = FF
                          00051
                          00052 ;  0 := v W0 -> 1
 0035 86 0D           [3] 00053          stx    W0        ; X = 80
 0037 85 0E           [3] 00054          sta    W0+1      ; A = FF
 0039 60              [6] 00055          rts
 003A                     00056 Test:
 003A A9 00           [2] 00057          lda    #0
 003C 85 16           [3] 00058          sta    S1
 003E                     00059 2:
 003E 20 0029         [6] 00060          jsr    99b
 0041 C6 16           [5] 00061          dec    S1
 0043 D0 F9 (003E)  [2/3] 00062          bne    2b


Instead of 128, it yields -128.
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Chromatix
PostPosted: Wed Sep 23, 2020 12:45 pm 
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Surely -1 - 127 = -128? So it gives the correct answer.
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BillG
PostPosted: Wed Sep 23, 2020 12:49 pm 
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You are right.

It is too early.
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BillG
PostPosted: Wed Sep 23, 2020 2:13 pm 
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Updated testbed so that:

1. Both S1 and the result appear in registers for easier interpretation
2. Result rises monotonically through all 256 values of S1

Code:
                          00031 ; W0 := -2 - S1;
                          00032
                          00033 ;   ;  0 := v W0 -> 1
                          00034 ;   ;  1 L r 2
                          00035
                          00036 ;      ;  2 L c -2 -> 3
                          00037 ;      ;  3 - v S1
                          00038
                          00039
                          00040 ;  1 L r 2
                          00041 ;  2 L c -2 -> 3
                          00042 ;  3 - v S1
 0029                     00043 99:
 0029 A5 16           [3] 00044          lda    S1        ; A =
 002B 49 7F           [2] 00045          eor    #$7F      ; A =
 002D 18              [2] 00046          clc
 002E 69 7F           [2] 00047          adc    #<65407   ; A =
 0030 AA              [2] 00048          tax
 0031 A9 FF           [2] 00049          lda    #>65407   ; A =
 0033 69 00           [2] 00050          adc    #0        ; A =
                          00051
                          00052 ;  0 := v W0 -> 1
 0035 86 0D           [3] 00053          stx    W0
 0037 85 0E           [3] 00054          sta    W0+1
 0039 60              [6] 00055          rts
 003A                     00056 Test:
 003A A9 7F           [2] 00057          lda    #$7F
 003C 85 16           [3] 00058          sta    S1
 003E                     00059 2:
 003E 20 0029         [6] 00060          jsr    99b
 0041 A4 16           [3] 00061          ldy    S1
 0043 88              [2] 00062          dey
 0044 84 16           [3] 00063          sty    S1
 0046 C0 7F           [2] 00064          cpy    #$7F
 0048 D0 F4 (003E)  [2/3] 00065          bne    2b


The next version will also calculate the result using a more conventional algorithm and point out any differences.
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Druzyek
PostPosted: Wed Sep 23, 2020 2:46 pm 
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The 1802 is one I was kind of interested in too, partly for the quirkiness of it. Someone gave a talk at the Silicon Valley Forth Interest Group (SVFIG) about a Forth for the 1802, but I can't find the link. Apparently, even traversing a normal-sized dictionary to look up a word took a painful number of seconds due to the crazy number of cycles each instruction takes. If I'm not mistaken, this is due to its 1-bit ALU. There were improved 1805 and 1806 models that added BCD arithmetic and subroutine support, among other things, though not sure this qualifies for your list since it may have come out after the 70s.

A few other chips to consider:

Signetics 2650 - 8 bit CPU from 1975. Interesting "minicomputer" type addressing
Signetics 8X300 - 8 bit, 1976. Very strange architecture with 16 bit instruction bus and only a handful of instructions. Number of bits to shift is part of the instruction for example
National Semiconductor SC/MP - 8 bit, 1974. One model, INS8073, has serial communication and a BASIC interpreter built into the chip
TMS9900 - 16 bit, 1976. Used in TI-99 computers
Harris 6120 - 12 bit, late 1970s? PDP-8 on a chip
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BillG
PostPosted: Wed Sep 23, 2020 3:19 pm 
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I have a soft spot for the 1802 as well.

* I bought a COSMAC Elf 2000 at one of the Vintage Computer Festivals http://www.sparetimegizmos.com/Hardware/Elf2K.htm
* A dearly departed friend gave me an 1802 Membership Card and an unfinished ELF clone
* A current friend experimented with the 1802, MicroDOS and recovered a PL/M compiler https://web.archive.org/web/20191002225 ... index.html
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Martin_H
PostPosted: Wed Sep 23, 2020 10:11 pm 
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Druzyek wrote:
If I'm not mistaken, this is due to its 1-bit ALU.

It does indeed have a serial ALU (which seems crazy), but the processor's design center was for low power environments.

Druzyek wrote:
TMS9900 - 16 bit, 1976. Used in TI-99 computers

I have a TI-99/4a in my retrocomputer collection, and the TMS9900 is a decent microprocessor, especially when paired with the TMS9918. It really was 16 bits in the 8 bit era, and its ISA feels more like a minicomputer than a typical microprocessor of the era. TI also had interesting ideas to extend memory by giving support chips their own RAM or ROM, so its address space felt less cramped.

Unfortunately it got a bad rep due to TI's poor decisions with the TI-99/4a. I've heard the TI-99/4a was supposed to be a game console, hence the tiny amount of RAM on the CPU bus. But the home computer boom made TI quickly rework it into a personal computer, while using the TMS9918's video memory to store BASIC programs. The results were less than stellar and gave the machine a bad rep.

But if you are using a program out of a ROM, or have expanded RAM, the computer compares favorably with even the C64 which came years later. Slightly better decisions from TI could have produced a real winner.
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BillG
PostPosted: Wed Sep 23, 2020 10:54 pm 
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Martin_H wrote:
I have a TI-99/4a in my retrocomputer collection, and the TMS9900 is a decent microprocessor, especially when paired with the TMS9918. It really was 16 bits in the 8 bit era, and its ISA feels more like a minicomputer than a typical microprocessor of the era. TI also had interesting ideas to extend memory by giving support chips their own RAM or ROM, so its address space felt less cramped.


That is because the TMS9900 is a microprocessor implementation of the TI 990 minicomputer.

I am still undecided just how fast the 9900 could be in a "proper" design.

https://ia801205.us.archive.org/14/item ... l_1977.pdf

Appendix A goes into excruciating detail about the time taken by each instruction. It speaks in terms of machine cycles. A machine cycle consists of two clock cycles. A common clock rate for the 9900 is 3 MHz.

Martin_H wrote:
Unfortunately it got a bad rep due to TI's poor decisions with the TI-99/4a. I've heard the TI-99/4a was supposed to be a game console, hence the tiny amount of RAM on the CPU bus. But the home computer boom made TI quickly rework it into a personal computer, while using the TMS9918's video memory to store BASIC programs. The results were less than stellar and gave the machine a bad rep.


TI designed the 99/4 for a version of the 9900 with an 8-bit bus interface, much like the Intel 8088 is to the 8086. But the processor was late forcing hasty modifications made to use the 16-bit processor in the 99/4. Each memory access was broken down into two 8-bit accesses by external hardware.

Martin_H wrote:
But if you are using a program out of a ROM, or have expanded RAM, the computer compares favorably with even the C64 which came years later. Slightly better decisions from TI could have produced a real winner.


TI has plans to make a large share of the money from royalties selling program cartridges rather than machine sales. When some developers balked, later versions of the machine refused to run "unauthorized" cartridges.
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BillG
PostPosted: Wed Sep 23, 2020 11:09 pm 
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BillG wrote:
The next version will also calculate the result using a more conventional algorithm and point out any differences.


Testing with values of the constant clustered around "trouble spots" like 127, 0 and -128 passed for all 256 values of S1.
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BillG
PostPosted: Thu Sep 24, 2020 7:21 am 
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This is my understanding...

Please refer to the following page for an explanation of Excess 127:

http://www.mathcs.emory.edu/~cheung/Cou ... ess-n.html

This table illustrates the process:

Code:
Number  2's compl   Number eor $7F    0 - Number     Excess 127

-128       $80           $FF            $0080           $FF
-127       $81           $FE              $7F           $FE
-126       $82           $FD              $7E           $FD
   :
   :
  -2       $FE           $81              $02           $81
  -1       $FF           $80              $01           $80
   0       $00           $7F              $00           $7F
   1       $01           $7E              $FF           $7E
   2       $02           $7D              $FE           $7D
   :
   :
 125       $7D           $02              $83           $02
 126       $7E           $01              $82           $01
 127       $7F           $00              $81           $00


The first column is the number as we write it in signed decimal form.
The second column is the number in two's complement form. This is what is stored in S1.
The third column is the number Exclusive OR'ed with $7F.
The fourth column is the negative of the number. One way to get this is to subtract it from 0.
The fifth column is the negative of the number in Excess 127 form. To convert it back to two's complement, we have to subtract 127.

Notice that Number eor $7F is the same as 0 - Number in Excess 127 form...that is the secret sauce...

Constant - S1 is the same as Constant + (0 - S1)

which is the same as Constant + ((Number eor $7F) - 127)

which is the same as (Constant - 127) + (Number eor $7F)
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BillG
PostPosted: Sat Sep 26, 2020 12:43 am 
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barrym95838 wrote:
Perhaps we could make a rough estimate of relative code density by comparing implementations of fig-FORTH? I see 1802, 6502, 6800, 6809, and 8080 (no Z80 unfortunately). The versions probably aren't quite identical in features, but should be close enough to at least get some initial data points.


Some time ago, I found and bought a used copy of Threaded Interpretive Languages. Some time later, I wrote an implementation for the x86, then ported it to the 6800 and AVR.

Some time after that, I found and read the FIG-Forth documents. The 6502 and 6800 versions implement slightly different Forth models. The 6800 version uses pointers to two bytes before a word, pre-incrementing them before use because that was more efficient. That was exactly what I had decided to do in mine.

Still, those implementations may be a useful tool for comparing the two processors.
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barrym95838
PostPosted: Sun Sep 27, 2020 7:31 am 
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BillG wrote:
The 6800 version uses pointers to two bytes before a word, pre-incrementing them before use because that was more efficient. That was exactly what I had decided to do in mine.

Still, those implementations may be a useful tool for comparing the two processors.

Charlie uses that technique in his DTC PETTIL FORTH too. I think it might be the most meticulously optimized NMOS 6502 FORTH I've ever seen. He even includes a customized and optimized SWEET16 interpreter.
Code:
; PETTIL NEXT routine
ip      =       next+5
next   inc ip
       inc ip
nexto  jmp ($CAFE)

He uses a compiler trick for page crossings which I don't completely understand.

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BillG
PostPosted: Sun Sep 27, 2020 10:44 am 
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barrym95838 wrote:
Code:
; PETTIL NEXT routine
ip      =       next+5
next   inc ip
       inc ip
nexto  jmp ($CAFE)

He uses a compiler trick for page crossings which I don't completely understand.


There is much context information missing.

The first "inc ip" would appear to morph the second one into "inc ip+$100" which may or may not be meaningful depending upon what is in the next page.

But if this code is in the zero page, which you did not exclude, things are a bit more interesting. The two "inc ip" instructions increment the low byte of "$CAFE" twice making it $CA00 the first time through. It becomes $CA02 the second time, etc. This does make sense in the Forth world for executing successive words starting at $CA00. Is there code somewhere which stores an address at nexto+1 and nexto+2?

Edit: corrected a couple of errors...
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barrym95838
PostPosted: Sun Sep 27, 2020 2:53 pm 
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Sorry about the missing context. Charlie's NEXT resides in ZP, so the INC IPs increment the $FE in $CAFE.

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