I've been curious about building a 6502 system with a pair of VIA's, rather than the usual 6551 paired with VIA's. The idea is two fold: first, side step the 65C51 bug. second, the hardware forces you to try self-hosting, rather than being reliant on a host PC. As luck would have it, there was an auction for an APATCO NCS-EB50 on eBay which has this hardware configuration. So I purchased it to give it a try.

But there is a problem. The documentation included with the NCS-EB50 is thin and missing obvious information like a parts list. I assume that's because APATCO intended for the PCB to be an add-on to their NCS-2056T breadboard computer kit, rather than a standalone product. However, the NCS-2056T is perpetually out of stock, and APATCO's contact us email link is broken. So I am somewhat on my own with the PCB.

The documentation did include a memory map and a schematic, so I am using the latter to build a parts list. I've also uploaded everything to Google drive including my parts list in progress.

See: https://drive.google.com/drive/folders/ ... sp=sharing

Looking at the memory decoding logic, it looks identical to Daryl Rictor's SBC2.

But there are some things I find odd about this schematic compared to other 6502 SBC's I've seen:

* The diodes for the VIA's IRQ line are 1N5817 rather than the usual 1N4148 or 1N914. I have a bunch of the latter so I am wondering if I can substitute?

* Each IC has a pair of capacitors in parallel between Vdd and ground. I assume this is for decoupling the IC's. Normally most schematics only have a single 0.1 uF capacitor. But the VIA 1 for example has C7 0.047 uF and C11 1.0 uF.  Likewise the RAM has C3 performing a similar function, but it has a value of 0.056 uF!

* If the small capacitor is a decoupling cap, what is the purpose of the 1.0 uF?

* Resistors R3 through R13 look like pull up or pull down resistors, but the 3K value is slightly less than the 3.3K used in the SBC 2. Is this reasonable? But that raises the question why 3K versus 10K which I've seen used as pull ups in other applications?

* The data sheet claims you can use either a W65C02 or a W65C816S. But I thought the W65C816 wasn't a drop in replacement to the W65C02 due to asserting the high address lines on the data bus. Would this actually work?

* Having the choice of a TTL oscillator or crystal oscillator circuit is a bit odd.But I guess it is related to the educational aspect of the kit.

Any small signal Schottky diode will work. The 1N914 and 1N4148 have too much forward drop to reliably pull IRQ down to a solid logic zero.


Usually, an arrangement such as that (theoretically) improves performance a bit by reducing voltage fluctuations at Vcc. I personally don't think the 1.0 µF capacitor is doing all that much in that regard.


3.3K is customary for pullups. 10K will work but increases vulnerability to noise.


There are some pinout differences that may trip you up. I suggest you stick with the 65C02.


I'd go with the oscillator, which must generate CMOS, not TTL, output. Crystal oscillators can be touchy and sometimes won't run in a stable fashion if operating conditions aren't right.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thank you for the detailed response BDD.

I have almost enough to build this board with parts lying around the house. But I only have 0.1 uF decoupling caps, which are the values I normally use. I'm tempted to use those instead of the 0.047 and 0.056 uF values they call for.

Also can you mix LS and HC logic? Most of my spares are in the LS family, but I have a 74HC30 I could put to use here.

Sounds like a small difference to me: a bigger difference might be if they are a different kind of capacitor, which could affect the frequency reponse.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks BigEd and Garth.

The 0.1 µF caps will work fine. Use X7R MLCCs if possible.


An HC device's outputs will have no problem driving an LS device's inputs to a solid 0 or 1. However, as Garth noted, an LS device's outputs are not guaranteed to rise to the CMOS equivalent of logic 1, which is typically 3.5 volts minimum in a 5 volt circuit. It might work...or might not. Or it might work for a while but normal device temperature rise during operation may eventually cause the unit to become unstable or go belly-up.

If you must mix logic families I suggest you use HCT devices, whose inputs operate at TTL levels and thus are compatible with LS logic. Best results are achieved when a single logic family is used throughout.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yes. I have done it on my Ruby 6502 system when I looked at moving to the 65816... To do it correctly there ought to be a single jumper but I never bothered - the result is that the clock output on the 65C02 gets pulled to +5v via a 3.3K resistor. This is a signal input on the '816 that normally needs tying high. Having a jumper would prevent this happening, but in didn't seem to make any difference to the operation of my board when I reverted back to the 6502. I don't use that clock for anything anyway. (I'd modded the PCB rather than spin up a new one - if I were to design a new one then I'd put in a jumper). I've not checked that schematic, but maybe there is a jumper?

There is no issue with the top 8 address lines being output during the low half of the clock cycle.

Get what CPU you want, but please get it from a reliable source - e.g. Mouser. There is no reason to buy them from weird ebay sellers because they're still being manufactured and sold new.

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

@all, thanks for the feedback. I'll try the mixed HC and LC and see what happens.

The reason I have LC logic is I live near a good old fashion electronics store called You-do-it electronics, and that's what they carry. They are a bit like stepping into a 1970's Radio Shack (in a good way). I also mail order from Mouser and Digi Key as well.

@Gordon, I looked at the schematic and I didn't see a jumper to a pull up. Which CPU pin would need it?

the '816. It's the ABORT pin - pin 3.

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Thanks. Looking at the schematic, they have it pulled up with a 3K resistor and available on their expansion bus. But otherwise unused. They labeled it PHI10/ABORTB as well.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Not necessarily. I agree with BDD's point, and will cite another.

In 6502 and 65C02 systems, write data from the CPU and read data from the system typically remain on the data bus (due to capacitance) for a long time -- essentially an extra 1/2 cycle -- after Phi2 falls. And it wouldn't be surprising if some systems will fail without a few extra ns of write data hold time -- the designer has knowingly or unknowingly created a design which depends on it.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html