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PostPosted: Wed Aug 12, 2020 9:02 pm 
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Ok, so I might be losing my mind here and I know there is not really any value in this since these machines are very available today but . . . .

In the last couple of years I have enjoyed building a couple of "modern" compatibles of the MSX (Sergey's Omega project), an Apple 2 org 0 reproduction, and the Sinclair Spectrum (Harlequin 128K project), and that left me wondering . . Would it be possible to recreate the C64 and/or VIC-20 in this fashion. Could one create a new PCB that is close to 100% compatible using only readily available parts with as few as possible custom ICs?

I am very sure that a Vic-20 compatible could be created with modern sram and eproms, a WDC 65c02, etc . . . only needing a single 6560 vic chip (and perhaps that could be replaced with TTL logic like the harlequin 128). I am also fairly sure that a 64 could be recreated needing only a VIC 2 and SID, using logic (GALs/CPLDs/TTL perhaps?) to allow the use of a 65c02 rather than the 6510, and perhaps finding a way to substitute 6522s for the harder to find 6526s with support logic filling in the gaps. I would prefer to avoid FPGAs in this as it is kinda cheating, and has already been done about eleventy million times ;)


I have not done any detailed work on this yet, right now it is just a passing thought, and will likely stay that way until I get my Apple 2 WiFi card done, but I thought I would put the idea out there to see if any one else had thought of this (or better yet attempted it)

Dan W.

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PostPosted: Wed Aug 12, 2020 9:20 pm 
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Location: Scotland
Hello,

Have you seen the Commander-x16 project? It's effectively (from what I gather) a Vic-20 with 65C02 and some banked RAM, however it does have FPGA video.

There is also a PET replica too - https://www.thefuturewas8bit.com/mini-pet.html

So plenty of scope to make a look-a-like yourself... Start drawing!

Cheers,

-Gordon

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See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/


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PostPosted: Wed Aug 12, 2020 9:23 pm 
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drogon wrote:
Hello,

Have you seen the Commander-x16 project? It's effectively (from what I gather) a Vic-20 with 65C02 and some banked RAM, however it does have FPGA video.

There is also a PET replica too - https://www.thefuturewas8bit.com/mini-pet.html

So plenty of scope to make a look-a-like yourself... Start drawing!

Cheers,

-Gordon


I actually have been following that project -- and have built a couple of "non compatible" computers myself. I suspect for me, the Vic would be a "warm up", heading to a 64. Unless I get brave and start working on replicating 6560 with TTLs or CPLDs. :)

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PostPosted: Wed Aug 12, 2020 9:32 pm 
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and . . . I just found this. This is what I get for falling behind on the forums :)

http://www.6502.org/users/sjgray/projec ... index.html

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PostPosted: Thu Aug 13, 2020 11:29 am 
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I was recently pointed at this by fhw72:

https://www.forum64.de/index.php?thread ... -gebastelt

It's a modern Commodore 16 PCB using SMT. The expansion port connector must come from an old board but many of the other components are available today.


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PostPosted: Thu Aug 13, 2020 12:56 pm 
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unclouded wrote:
I was recently pointed at this by fhw72:

https://www.forum64.de/index.php?thread ... -gebastelt

It's a modern Commodore 16 PCB using SMT. The expansion port connector must come from an old board but many of the other components are available today.



yup, that is almost exactly what I was thinking -- but with (eventually) the C64. I need to finish up what I am working on now, but I do think I will build a prototype Vic-20 PCB as a proof on concept at some point in the near future and then see if it is possible for the 64.

Thanks for all of the feedback!

Dan W.

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PostPosted: Mon Nov 16, 2020 2:14 pm 
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I have made some progress on the VIC-20 clone. All is well, except I have some kind of timing problem. I notice it most when the screen is scrolling -- it appears that when the CPU is in a tight loop it has occasional read problems. See the pic of the screen shot. The Basic program prints "TEST TEST TEST TEST" in a loop and it is possible to see the corruption as it scrolls up the screen. Note the bottom line always is correct, and it corrupts as it scrolls up. I have done several other tests and I am pretty sure (not 100% though) that the problem is on read, not write.

I am working though this but, if anyone has any ideas about what I missed here it would be appreciated!!

See attached pictures and schematic.

Attachment:
vic1.jpg
vic1.jpg [ 375.63 KiB | Viewed 962 times ]

Attachment:
vic2.jpg
vic2.jpg [ 360.49 KiB | Viewed 962 times ]


Attachments:
vic2020Schematic.pdf [632.81 KiB]
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PostPosted: Mon Nov 23, 2020 12:49 am 
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Search for the SixtyClone project, which is close to what you describe.

Jim


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PostPosted: Fri Nov 27, 2020 9:07 pm 
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I finally found the problem (at least it seems to be solved). . .

Looks like CE was getting asserted too soon on U12. To fix it, I changed S02 to be just CPU02 and not an OR of SO0 and CPU02, and I added a gate to introduce some delay after U9D. It has been running for several hours with no issues.

(See new schematic -- attached)

I have ordered new PCBs to confirm that it is totally fixed, and I found a company that prints custom key caps, so I ordered a set of petscii keycaps to finish it off. Assuming that everything passes the tests, I will post all of the gerbers and the keycap templates in case anyone else is interested in building one.


Attachments:
Mainboard_SCH.pdf [638.72 KiB]
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