I’ve been planning on using an PC ISA bus backplane for a 65816/65832-style computer. The ‘832 would be located as an ip core in an FPGA carrier board. The ISA bus will be repurposed with 40 address lines and 32 data lines in a multiplexed address / data fashion. However, when the /REFRESH signal is high it will be used to indicate an 8-bit ISA compatible access. This allows 8-bit ISA cards to be used by the computer. For a new style bus access /SMEMR, /SMEMW, /IORD, /IOWR will be inactive, but /MEMR, /MEMW in the extended bus will be active.

Unfortunately, there are not enough I/O’s on the FPGA board to support the full ISA bus as desired. So, I’m left with trying to come up with a means of multiplexing I/Os to support everything. There are about 50 I/Os available.
24 address + 16 data takes up 40 I/Os. Also needed are reset, read/write, and ready. One idea is to have IRQ’s and DMA lines multiplexed onto the data bus periodically so they can be sampled when safe to do so. This would require inserting an extra clock cycle every few bus cycles. Rather than having IRQ’s respond at the beginning/end of an instruction it would end up every fourth instruction for instance.
A second possibility is to use fast shift registers to read the IRQ / DMA signal lines. This is appealing because multiplexors on the data bus are then not required. It may also offer lower latency than the previous idea.

I think I’m just going to have the processor read a specific address to get at the interrupt / DMA request lines. So, periodically the core outputs $FF…FFFC as the address. This address is internally decoded to form a select signal /IDS. So for one osc period (31 ns) /IDS will be active and the interrupt / DMA signals placed on the data bus. There will be a control register in the processor to specify the frequency of IDS in terms of bus cycles. Since a bus cycle is 122ns IDS would consume 20% of the bus bandwidth if active on every cycle.

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Bus Signals

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Nice one Rob - I keep forgetting that you've already tackled the '816 as a core for FPGAs.
Doing the '832 could be interesting!

I have already an ‘832 core (called FT833) but it’s got only an 8-bit data bus, Interfacing to the bus isn’t very well done so I’ll be improving it and modifying it to allow 32-bit data transfers. It needs to be modified to poll for interrupts and DMA as well for this project. The core does make use of an instruction cache so it fetches all the bytes for an instruction in a single cycle. The ‘832 core is about 11,000LUTs so it fits in many newer FPGA parts.

While it follows the '832 spec closely the '832 core has additional features such as extra-long data addressing modes, allowing the use of 32-bit addresses.

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Deviating from the idea of using an FPGA based '832 core after looking at how much work would have to be put in to modify the core for use.

Tonight, for a cpu board I’m thinking of using an 82C206 chip which is an PC AT motherboard chip that includes most of the peripherals for an AT machine. This 82C206 chip would be used in combination with a 65C816, so would require a little bit of logic for interfacing. The 82C206 would take care of the interrupt and DMA signals on the bus. Only 8-bit DMA would be supported as the 65c816 has only an 8-bit bus. A hold acknowledge and an interrupt acknowledge signals would need to be generated for the chip.
Fortunately, these can be done with relatively simple state machines.
On a hold the RDY line to the 65C816 would be pulled low. The next cycle the BE line would also be pulled low to tri-state the 65C816 signals and HLDA signaled active. The DMA transfer would then take place. When the HOLD request line goes inactive RDY will go high and BE will go high enabling the 65c816 accesses.
Two INTA pulses are required to release the interrupt byte from the controller. To read the byte a memory load instruction would be executed at the I/O address of the controller. The INTA signal would be pulled low and RDY pulled low for the first cycle. For the second cycle when INTA is low ready is high allowing the byte to be read. I think this can be done with just a counter or shift register.

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After last night’s diversion, I started working on the bus interface unit for a 64-bit core. Everything for this project seems to be revolving around the bus at the moment. With a good bus interface unit, a number of different processing cores could be interfaced. It’s somewhat tricky as the interface has to provide access to both an external system bus and internal bus, so there’s some code replication. The external bus is a multiplexed address / data bus, Data bus is 32-bits. The internal bus is non-multiplexed, 64-bit data. It’s made trickier again by the need to support both data and instruction access. And again by the need to support dram access as well as ordinary access.
The bus interface unit also takes care of unaligned access by running multiple bus cycles, and takes care of sign extending read data.
There may be issues with unaligned access read / writes spanning a 4GB boundary depending on how slaves are implemented. The upper 8-bits of the address (32 to 39) outputs the previous value when data is placed on the databus. This may not be the current value if this part of the address bus incremented due to a 4GB boundary crossing. If the slave is using ALE to latch these address bits it doesn’t matter it’ll get the correct address, however if the slave assumes these address bits remain the same and doesn’t latch them then it will have an effect.
The module is about 560 LOC.

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Mapped out the bus signals onto the FPGA board signal lines. It turns out significantly more FPGA I/O’s are available than I though initially. I was able to map all the bus signals using separate signal lines for IRQ’s and DRQ’s. This is good because it will simply things. There are some signal lines still available so I’m wondering about the distribution of components. It’s conceivable that an SBC computer card could be made with video, keyboard, and mouse all on the cpu card.
However, I’d prefer a separate video board in the system that would house it’s own GPU and accelerator components.

Got most of an 8-channel DMA controller coded. About 300 LOC. All eight channels operate identically. It’s fairly rudimentary, nothing fancy. It supports the three modes of operation available with the 8237 chip for each channel. One-off transfer, block transfers and demand transfers. Each channel has base and current registers for the address and transfer count. Transfer addresses may either increment, decrement or remain constant.

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Spent some time studying and coming up with a circuit interfacing interrupts for an '816 processor.
In emulation mode interrupts are handled via ROM vectors as normal. The interesting part occurs for interrupts handled in native mode.
The encoded interrupt level (one of sixteen) is used to form part of the vector address. Vector targets are spaced four bytes apart. This
then gives a target area of 64 bytes. The upper 8 bits of the vector address are stored in a latch. This allows any page in the lowest 64k
bank of memory to be used as a target address.
Bits 6,7 of the vector are fed from an external eight-bit addressable latch which serves multiple purposes.
I think the following circuit should work. (Sorry about the color, I haven't figured out how to get the CAD program to output mono.)

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It looks to me like you took a screenshot of the Kicad schematic window?
If you instead go to File -> Plot, you can create a PDF of the schematic, and one of the options is "Output mode" (Color | Black and white).
Then you can either attach the black & white PDF directly, or you can take a screenshot of the open PDF if you only want to show a subset.

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Want to design a PCB for your project? I strongly recommend KiCad. Its free, its multiplatform, and its easy to learn!
Also, I maintain KiCad libraries of Retro Computing and Arduino components you might find useful.

Yes, it is a KiCAD schematic. Thanks for the suggestion, I was able to plot a monochrome image of the board schematic so far. I still need to add RAM, ROM, and a uart to make it a SBC.

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