The Wiki's article about the 6502, https://en.wikipedia.org/wiki/MOS_Techn ... 1_and_6502, states that the 6501 was not completely pin compatible with the 6800. The 6501 doesn't support tri-state output, therefore it, unlike the 6800, can't be used with for instance, DMA. Commodore had to add tri-state support in their 6510/8510 and 7501/8501 because the C64 and C264 use DMA for video output. Another incompatibility is pin #2 which is HALT for the 6800 and READY for the 6501. IMHO they have quite different meaning. So I can't understand why VIP told that the 6800 and 6501 were pin compatible. Could anybody help me to understand this matter?
Bill Mensch in his Oral history told that there were big plans around the 6501 and this contradicts Chuck Peddle Oral history where he stated that there were no plans to use the 6501 instead of the 6800. Indeed it will be very interesting to read some information directly from Rod Orgill. Is there some text available from him somewhere?
Thank you

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I don't think I've ever seen anything from Rod Orgill. (Edit: evidently I am mistaken.)

Halt on the 6800 is active low, and RDY on the 6502 is active high, so they do have the same sense: high to run, low to stop. However, RDY only slows down read cycles, so it has the limited use of allowing access to slow ROMs (unless the application builds a complex memory interface - and that wasn't the target type of machine.)

I see in Donald Hanson's giant blueprints (not public) that there's a DBE pad in between Phi2 and RnW, and that a DBE-derived signal internally is also labelled TSC. But indeed it only tristates the databus drivers - there is no provision to tristate the address bus. Again, it might be true that this has some limited applicability in some subset of 6800 applications. Indeed, surely the majority of low-end applications would not have DMA - it's not the sort of thing you put in point-of-sale machines or soda dispensers.

Edit: some notes on the blueprints here:
https://web.archive.org/web/20200624185 ... atic_Notes

I'd be careful of reading too much into Wikipedia's exact content: it's subject to change, there are opinionated people around, some of whom are mistaken, and many would-be contributors are put off by the edit wars. It can be useful when treated with caution, and especially when the references are followed up.

Thank you very much.
Is there any link to the aforementioned Rod Orgill's text?
Ready signal is used in the C264 series during video DMA, it allows three write cycles (it is the maximum for the 6502 instructions) before the DMA starts. Ready stops the CPU only on a Read cycle.
It looks like that for the differences between the 6501 and 6800 Wikipedia is almost correct: Ready functions not the same as Halt and there is no tri-state for address lines. I couldn't resist editing Wiki a bit. I have just added "from the address bus outputs" to the phrase "The main change in terms of chip size was the elimination of the three-state bus".
I don't know how often the 6800 based system used DMA but the 6501 can't be installed instead of the 6800 if the DMA or something other, which requires tri-state, was used. So I must conclude that the 6800 and 6501 were not 100% hardware compatible.

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Some interesting detail in the article "2½-generation μp's-$10 parts that perform like low-end mini's" ("Experience with first- and second-generation μp's has produced a round of MOS units fine-tuned to deliver most performance/dollar.") in the document "EDN_Sep_20_1975_6502" where I see a section "SIMPLEST POSSIBLE LOOP" and the text "Rod Orgill of MOS Technology says this program happens to contain the worst case timing for the μp as it asks the PC (program counter) to generate all carries when going from FFFF to 0000."

I've attached the document: it's a minimal breadboard bringup of a new micro.

Edit: ah, I see this document was already referenced in the wiki article, and there's already a link to an archived version!

Edit: ah, indeed the document had already been referenced over in the head post of that old thread.

Thank you very much. It is a really interesting article though it has little from Rod Orgill. It has a very interesting cite However neither Chuck Peddle, nor Bill Mensch gave any details about the planned 16-bit developments later.

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I think what they mean by pin-compatible is that, in redesigning your application to use a 6501 instead of a 6800, you will not need to change the pinout of the CPU socket. You will need to change other things, at a minimum the contents of your ROMs. Whether you would need to add external tri-state buffers on the address bus, driven by the signal also being sent to pin 39 on the CPU socket (not connected on the 6501), depends on whether you need that feature or not. If you don't use that it's quite possible that you might simply be able to unplug and replace the CPU and ROMs.

(I'd imagine that a lot of applications don't need to tristate the address bus, or the 6500 team, who had plenty of experience with the 6800, would have included that feature. Typically engineers remove stuff like this from clean-sheet designs because the cost can't be justified, rather than because they wanted to randomly remove functionality.)

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With Bill Mensch's comments at VCF-West, I am surprised Peddle said there were no plans for the 6501. Stealing sockets sounds like a very valid sales plan in the 70's. And, I agree with Curt, few machine controllers used DMA or needed to tristate the bus. As such, it was an easy feature to ditch to save die space (and get wafer yields up). Chuck's comment just doesn't make sense, because they had to know Moto would be on their backs over a pin compatible footprint, so why invite the legal heat if there's no value in it. The only valid reason I can see is that management decreed it because they were not confident people would design around the '02, and being pin compatible meant less risk for designers who were building the SBCs.

Jim

It does indeed, so possibly someone did have this idea and Peddle forgot or never knew about it. (Remember, the interview where he said this is almost forty years later.)


Well, I'm not sure that they did "have to know" that. I don't think that "strategic incompatibility" was such a big thing in the chip market of the day (though, then again, it certainly was in the mainframe market!).

But if they did know, and they were really thinking ahead, there was a good reason to make the 6501. Remember, they were not sued over the 6501 alone, but over everything Motorola could find that had any bearing on the 6502; Motorola would have probably been happiest to have killed the 6502 as well. From the interview (p.40, emphasis mine):


So it turned out to be a tactic that lost them almost nothing if they had no plans to push the 6501 as a 6800 replacement, yet saved them some money in the suit by giving them something else to put on the chopping block. I've no idea if they planned it this way, but from the above it sounds like they might have.

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Mmm, what's said there is also consistent with a rewriting of history: they hedged their bets, and now that they know what was successful and what didn't have any life in it, there's a temptation to tell the story that they knew what they were doing all along. (Very rarely do people know what they are doing all along, IMHO. Much more often, they get lucky. Hedging your bets is one way to increase your chances of being lucky.)

Given the cost back then of producing PCBs, it would be logical if you have a new low cost microprocessor, to make it pin compatible with an existing microprocessor so that (at least some of) your customers can minimise the costs of trying your microprocessor in their existing hardware designs...

Even if you get legal trouble later, if using this tactic gets you a foothold in the market and hence gets hardware engineers talking about your product, it’s a win.

Mark

Can anybody know something about other EDN articles about the 6502? It would be very good if they may be found somewhere on net... Thank you

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