I have a circuit that uses an 18CV8 PLD for the glue logic to interface with a serial communications controller (SCC). The 18CV8 is pin compatible with the 16V8, but adds a few additional features. The 18VC8 is no longer available, so I'm trying to see if I can replace it with a 16V8. I could use some help reverse engineering the ABEL source and translating it to CUPL.
Here is the ABEL source:
Code:
glue1 device 'P18CV8';
CLK,A2,A1 pin 1,2,3;
RIC_CS,RIC_RD,LBRES pin 4,5,6;
RIC_WR pin 7;
WREQA,DTRREQA,OE pin 8,9,11;
TXREQ4,RXREQ4 pin 12,13;
SCC_CS,SCC_WR pin 14,15;
SCC_INTA PIN 16 ISTYPE 'REG_D,INVERT';
SCC_RD,SCC_DC,SCC_AB pin 17,18,19;
C,Z,X,H,L = .C., .Z., .X., 1, 0;
equations
TXREQ4 = DTRREQA;
RXREQ4 = WREQA;
SCC_CS = RIC_CS;
SCC_INTA.C = CLK;
SCC_INTA := !SCC_INTA;
SCC_INTA.AR = !LBRES;
!SCC_RD = ( !CLK * !SCC_INTA ) + (!RIC_RD * !RIC_CS);
!SCC_WR = (!RIC_WR * !RIC_CS);
SCC_DC = A1;
SCC_AB = A2;
Most of it is straightforward and can be easily translated to CUPL. The part I am not sure about is SCC_INTA.
Code:
SCC_INTA PIN 16 ISTYPE 'REG_D,INVERT';
SCC_INTA.C = CLK;
SCC_INTA := !SCC_INTA;
SCC_INTA.AR = !LBRES;
It looks like SCC_INTA is a D flip-flop. I think that translates to 'SCC_INTA.d' in CUPL.
I don't think I need to explicitly specify the clock for the flip-flop in CUPL, so I can get rid of the 'SCC_INTA.c = CLK;' line.
I believe the ':=' is 'registered assignment'. I'm not sure what that means and if there is an equivalent in CUPL.
I believe the 16V8 does not support asynchronous reset, so I'll have to figure out an alternative. The CUPL Reference mentions incorporating the reset signal in product terms for a synchronous reset. Perhaps this is an option.
Unless I am mistaken, '*' means AND and '+' means OR.
Any advice or suggestions will be greatly appreciated.
Thanks,
Shawn