@revaldinho spotted something, which on the face of it looked suspicious, but on reflection is quite possibly fully compliant with the datasheet: a low-going glitch on RnW, fairly early in the cycle:



Anyone else seen such a signal?

I think in most designs, such a glitch will effectively be ignored because write enables are gated by phi2. (There's nothing essential about using phi2 for that, it's just convenient. What is essential is to allow a write pulse only after addresses, decoded chip selects, and RnW, are all stable.)

I've not seen this before, mysterious.
Is this the same system that had snowy video?
Any idea what instruction is executing when the glitch occurs?
Is there another master driving the write signal?
Does the glitch repeat? Could it be an issue with the scope data aquisition?

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Some answers, all more or less provisional:

It is the same in-socket accelerator, but we believe the glitch to come direct from the '816.
We don't presently know exactly what instruction was in flight.
There's nothing else driving RnW outside our trivial glue in the CPLD.
I don't know how repeatable this turns out to be.
We don't think the glitch is an artefact...

It would be good to investigate further...