I'm going nuts...

I used a 74HC374 D-Latch in my 6502 Breadboard Computer to set an 8-LED-Output sucessfully (at address 0x7000)

With the same principle I want to do a 3-digit-7-segment-display and give them the addresses 0x7001 (left), 0x7002 (middle) and 0x7004 (right).

When writing to 0x7000 only the LED-Output is triggered, the 3 segment-display don't get a clock and signal at CK keeps steady high.

BUT: the Seg-Display in the middle (and only in the middle) changes it Q-Outputs without any clock on its CK.

It's a riddle to me... I measured with my multimeter and my scope, what I could, but haven't found the error reason?

Do you have a clue?

I've made a video on youtube: https://www.youtube.com/watch?v=T7m3cLWXfLg

It's German. But the pictures spoke for themselves.

May the pictures on my blog (http://cool-web.de/elektronik/8-bit-bre ... usgabe.htm) help to investigate (or use Google translate on this, it's German too).

Any clue, any hint? I thought: No CK-Change = no Q-Change?

What I'm missing? I'g going nuts here...

Welcome! It might be omething more specific, but in the photo I don't see adequate decoupling caps: you need a cap like the one you have near to each of the chips, and you need a bigger one, an electrolytic, on the rails. (I say you need these: if you have an unreliable circuit, it's the best starting move, to clean up the power.)

Is this your schematic? If so, it needs to input Phase2 and use it to ensure that none of the '374 Ck inputs goes low except when Phase2 is high. That's because when Phase2 is low the CPU address lines are in transition, and their values are unreliable. This can cause undesired effects unless you ensure that the address lines get ignored when Phase2 is low.

Cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Okay, I've zoomed really deep in with my scope and found a 20 ns signal fall at the middle 374.
But only an the middle one, not on the left and not on the right one.

It's only 20 ns on low but this seems to be enough to trigger the 374er to update.

Yellow line on the scope is the NOT(A12 AND A13 AND A14) signal.
Blue line on the scope is NOT (A1 AND A12 AND A13 AND A14).

What's missing is the Phase 2 signal (aka Phi2). And yes, ignoring Phi2 will drive you nuts, because you will get symptoms that can vary, and sometimes may even disappear. But even though it may work sometimes, the circuit is broken until Phi2 is properly applied.

The importance of Phi2 is explained in my previous post. Do you have any questions? There are lots of knowledgeable people here who are willing to help you. It would be good to have a conversation. So far we only have stray observations from you.

Here is a simple change that shows the idea of what I'm saying in the previous post. None of the '374 Ck inputs can go low except when Phase2 is high. Unfortunately there's a lot of delay because we have three gates in series after the Phi2 signal, so it's not very good but it might work.

Here's another version that solves the delay problem, but it only protects 3 clock signals, not all four.

You could include both of these changes, and that would be alright. But instead you might want to consider using a decoder IC such as 74HC139 or 74HC138. Do you have any questions?

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The other thing that's missing is A15. As it is, that circuit will write trigger the flip-flops on any access to any address matching $Fxxx or $7xxx. You're going to want ROM somewhere in there, and you don't want your LEDs to change whenever it is read.

Also, the top output (labelled CK LED-Ausgabe (0x7000)) doesn't include A0 - A2 in its decoding. Whenever you write to any of the 7-segment outputs, it's going to trigger as well.

You're only including the address lines that you want to be 1 in your decoding. That's not enough. You have to include the 0s as well. You don't have to include all of them, but you do need to include enough that you don't get two devices responding to the same address.

Hello Friends,

thanks for your help so far.

I think the reason will bei the missing involving of the CPU clock and I will alter and check my circuit in this aspect.

Momentarily I read the docs from http://wilsonminesco.com/6502primer/addr_decoding.html . They are very helpful. Will read a little further. May I find more that's missing in my circuit.

@Dr Jefyll

will try the mod number 1.jpg. Thank you.

@John West

>> The other thing that's missing is A15. As it is, that circuit will write trigger the flip-flops on any access to any address matching $Fxxx or $7xxx. You're going to want ROM somewhere in there, and you don't want your LEDs to change whenever it is read. <<

Thanks for your advice, but you can't know this (that's standing somewhere in my blog in German). That's the way I want it. My ROM is WE always on high, so write protected. I drive the concept, that writing is only be allowed to the SRAM (lower 32 KB).

And that the LEDs also flash at 0xF*** is no problem. I don't think, I will use this high portion on ROM for programs. And the short Flashing when vectors (IRQ, Reset) are triggered are no problem.
And: the LEDs shall flash on every Adress between 0x7000 and 0x7fff (and 0xf000 to 0xffff). Because: if I don't use them for output, I can use them for debugging and see the last state that was outputted to any Output device.

I'll tell you, what the phase 2 integration will bring. But. Please don't stop your suggestions, if you have one. They are very informative.


BTW: My address table so far

I would not recommend mod number 1.

The WDC 65C02 guarantees only 10ns of stable address after the falling edge of PHI2. This is parameter tAH in the datasheet, the address hold time.

You cannot guarantee a clean final clock to the '374s with so much address decode happening downstream of the PHI2 gating. The delay through the logic is large enough that a new address may appear at the final gate before the gated PHI2 waveform. If that happens you will end up with a new variation of your existing clock glitching problem.

Gate PHI2 with the decoded address in the last logic stage, closest to the '374s for reliable timing (like mod number 2 for example). Hold timing problems can be difficult to debug.

I've measured the time, the NAND gates needs to operate:

Thats means the time between

A12 is going low (blue curve)
A12...A14 (NAND cascade) is going low (yellow curve)

and it is 15.4 ns.

In the going-high-phase the NAND-Cascade needs 16.8 ns.

Have to think about the timing will differ on solution 1 (phi2 into A12...A14) or solution 2 (phi2 into A0, phi2 into A1, phi2 into A2), which would be more effort.

@cool - John West is reminding you that the 374's will get clock pulses for read cycles as well as writes cycles. Your circuit only looks at the address, and it ignores the CPU's R/W signal.

This is an unusual way to control the 374's, but it's alright if you only write to them and never read from them. I assumed you were aware of this.

But I overlooked the other point John is making. Simply fetching code bytes from your ROM is a read operation, and your address decoding is such that even those reads might trigger the 374's. That's why A15 would make a difference -- to tell your circuit not to trigger during a ROM access. But R/W is probably a better way to prevent that problem.

I see how you're using A2, A1, A0, and I think you understand some combinations will actuate more than one 374 (for example if A2,1,0 = 111 then all three 374's will get actuated). It's OK to do it that way as long as you're careful not to do the wrong thing.

But your circuit absolutely needs to use the clock (Phi2). It also should use R/W or A15 (or both); otherwise it will be very tricky to avoid doing the wrong thing (ie, avoid reading code bytes from addresses that activate both the ROM and the 374's).

Please plan your changes accordingly. The circuit needs a serious re-think. If the clock is the only thing you change then the circuit will remain a booby trap, and you'll need to watch your step VERY carefully.

To fix the problem properly, have a look at some of the suggestions in Garth's primer. Have fun and keep us posted,

Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Finally I've found the reason for the strange behavior: propagation delay.
My TI 74HCT00N needs 5 ns for a gate pass, so the A12...A14 ist 20 ns befor A0, A1 and A2.
That is too much for the way I drive the 374er.
And I've found a solution.

Many thinking, measuring, testing.. I've documented it on my web page http://cool-web.de/elektronik/8-bit-bre ... ollten.htm
I've included translations buttons at the top of my weg page, so hit the US-flag (or your preferred language)

I've also made a video: https://www.youtube.com/watch?v=khpXpoqY3ok . Wait some time Youtube rendered the HD-Version... And it's German, not english.

Thanks for your suggestions. Learned a lot. Love the 6502primer. Very informative.