Ok, I have my SBC running well on a 4 layer board, with dedicated ground and power planes. 1 MHz clock speed.

I am now attempting to interface with a 65c22 VIA, off-board on a breadboard.

I can write to the via outputs successfully ONLY if I hardwire the VIA's r/w pin low.

My build uses a "ph2 qualified" r/w (credit to chromatix for the idea), such that chips only see the R/W go low on the second half of a cycle, when the data is guaranteed stable.

I have tried both this qualified R/W, and the signal direct from the 6502. Doesn't work. Only r/w hardwired low lets me write to the VIA.

My signals all look good.

On the logic analyzer, I show r/w low, both selects correct. Data bus only has 0's on it during the write (should be all 1's during the test). On the previous cycle, the correct data is on the bus as I load it into the accumulator. It just seems to vanish before the write. (at least according to my state measurement with the analyzer).

I haven't done much timing analysis with this analyzer (HP 1670E), so I'll be read up on how to do that tonight, as I suspect its relevant here.

Any ideas?

Some chips need to be that way, but I don't think 6522 is on the list.

Check the datasheet. I'm sure the 6522 wants its CS inputs stable BEFORE Phi2 rises, and I suspect that's also true for the R/W input. But I don't trust my memory ATM.

Too sleepy to look it up for you -- sorry! Off to bed now!

J.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Ok, solved.

I had to feed the VIA's PH2 with the actual system clock, not the PH2 from the processor.

Also, I had to use the R/W from the processor (the full cycle one)

I'm not clear exactly why this worked. I know the selects need to be valid before the rising clock edge, but to me using the actual system clock would be opposite of this, as it leads the PH2 out. The clock rises a little sooner.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The likely explanation is the MPU's clock outputs lag Ø2 in by an unspecified amount.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yes, the 65xx series peripheral devices are designed to be connected directly to the 6502 bus, ie. using the same Phi2 and R/W signals as the CPU. It's known as a synchronous bus interface. Only the chip-select signals need to be generated by glue logic.

This is in direct contrast to many other devices which adopt an asynchronous bus interface, with no explicit clock input and distinct /OE and /WE signals. It is these which must be Phi2-qualified.

I understand why the R/W being changed worked. Its the clock that confuses me.

Doesn't PH2O on the 6502 slightly LAG the PH2 in? Thus, by using the system clock for the VIA rather than PH2O, I'm giving the VIA slightly LESS time to react?

You said you changed two things to get it to work. One of them was not gating the R/W line. Does it really stop working if you go back to the old clocking arrangement?

But if it does, then you may be getting a different kind of timing violation than you expect, specifically for writes. The 6502 only keeps write data valid on the bus for a very short time after the end of Phi2 - this is known as the "hold time". The device receiving that data has to stop listening to the bus within that hold time, otherwise it might start seeing whatever goes on the bus next. Delaying the clock signal to a 65xx peripheral gives it less margin on that hold-time requirement.

Both the R/W and Clock changes are needed for it to work.

I get the data hold time thing now. Thanks!

BTW, on my 100MHz scope, I show the PH2o signal rising edge lagging the system clock by 9 ns. The falling edge only lags by about 4 ns.

That's a tight window between working and failing!

In some respects things are not as bad as they seem, at least for for 6502 and 'C02.

It's true those processors only drive write data onto the bus for a short time after the end of Phi2. The same is usually true for read data driven onto the bus by the system. But in practice the bus remains unchanged well after Phi2 falls simply because of its own capacitance. Of course that extra timing margin would easily be erased if another device were to immediately begin driving, but for 6502 and 'C02 it's usually true that nothing drives the data bus while Phi2 is low.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

This has turned out to be more educational than planned!

First, I actually spent time looking at the timing diagrams for the '22 and the '02.

Next, I for the first time tried doing timing analysis with my HP 1670e analyzer. Wow, I have been ignoring a great feature! My scope may give more info for specific signals, but being able to measure anything in the bus to any other thing in one screen is amazing!

Through use of that timing analysis, I see that by using the PH2O to clock the '22, I was 2 ns under the required hold time. By using the actual system clock, I am 6 ns over the required hold time. Still seems tight to me, and to be honest, I haven't really looked at what the trigger levels are for the analyser, but I imagine if I ignore the numbers I'm getting, graphically I can see the difference.

I'm curious what voltage thresholds I should be using here. All CMOS parts. Currently the analyzer is set for TTL.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?