diego2000 wrote:
When it's time to write the memory, the R/W pin goes LOW, the EPROM is set in high impedence state (because of the A15 pin goes LOW), but the data bus of the 6502 seems to remain in high impedence state or reading state.
The issue Ed mentioned may also have a bearing. But...
When do you sample the data bus?
Every cycle has two halves... the first half when Phi2 is low, and the 2nd half when it's high.
During the first half, the conditions you describe are NORMAL for a write cycle. The CPU remains high-impedance until Phi2 goes high. THEN is when you need to take your sample (if you're not doing it that way already).
If you continue to have difficulty please post a photo and a schematic. This will help us to advise you.
Cheers, and welcome!
ps- on this forum you may attach images to your post
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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