picosecond wrote:
Thanks for the welcome, BigEd and Proxy. Sometime soon I will get off my duff and make a proper greeting in the Introduce yourself thread. Here is a one-liner: I have worked professionally designing custom ASICs for more than three decades, but I have never designed a CPU.
ironically i'm quite the opposite, i have never worked in the Hardware Design/ASCI field, but i've made a dozen of custom CPUs over the last few years.
it's easier than you think, atleast when you don't follow any specific feature/instruction set, or make a RISC CPU... those things are just really easy.
picosecond wrote:
There are already numerous 65xx cores that can be used in FPGA applications but I think there is ample room for innovation. None of the cores I have looked at are particularly small. I think a minimal-area core is an interesting design challenge. And of course, the sky is the limit in the high-frequency / high-IPC direction.
and to be honest, i make Verilog code the lazy way. i build my circuits in a Logic Simulator and just click a button that says "Export as Verilog", put that throught Quartus onto my FPGA Dev board, and there you.
and I don't know how auto generated code compares to manually written code in terms of resources and efficency.
so I don't think i would be the best for that job. especailly since i use a completely different internal architecture that is much more resource demanding than the original 6502's.
only good thing about my architecture are the decreased cycle times... which is mostly because I technically have 2 ALUs in my CPU.
picosecond wrote:
For me, instruction compatibility with the original 6502 is not very interesting or useful without also having clock cycle compatibility. Since improved IPC is one of your goals I would forget about the original and start with the 65C02 as a baseline. Get that working on some FPGA dev board before adding new instructions/features. There are many design trade-offs to consider for this seemingly simple (but definitely not) project. For starters, do you optimize for embedded or external RAM? Do you emphasize portability or optimize for a specific FPGA family?
about the 65C02, i can easily expand my 6502 design to a 65C02 without any major changes to the circuit. this is also why i want to start with the 6502, because once i have that working i can add new features without having to worry about any of the existing 6502 stuff.
Cheap FPGAs often don't have a lot of BRAM so i always try to minimize the usage of it.
but i could put the Zeropage or Stack onto the embedded RAM as it would only take up 512 Bytes, and it could speed up cylce times even more (single cycle push/pull instructions, imagine that!).
though for most testing i use BRAM to save myself having to build a circuit to interface with external RAM.
and lastly, i have no idea how i could optimize code for a specific FPGA family. my FPGA Dev board is a Cyclone II but I'm currently looking into Lattice FPGAs because they are basically the cheapest on the market while still fitting a bit into them. (for example i designed a simple color VGA core that fits into this FPGA while only using ~60% of it, making it a very cheap VGA option for any 8 bit computer).
picosecond wrote:
If you are more interested in exploring instruction sets in simulation and less interested in ultimately building something these thoughts are probably not helpful. Maybe we find fun in the same things, maybe we don't. By all means, focus on what floats your boat.
so it was still helpful, though my current focus is to mainly get something working before i tackle any advanced versions of the 6502. (65C02, 65CE02, or something custom)
