BigEd wrote:
(welcome, picosecond)
Proxy wrote:
Also welcome, picosecond! I'm sorry your first post had to be on such a mess of a thread.
Thanks for the welcome, BigEd and Proxy. Sometime soon I will get off my duff and make a proper greeting in the Introduce yourself thread. Here is a one-liner: I have worked professionally designing custom ASICs for more than three decades, but I have never designed a CPU.
Proxy, I don't think your thread is a mess and I am not put off by a little squabbling. If I may, here are some poorly organized thoughts on your project:
There are already numerous 65xx cores that can be used in FPGA applications but I think there is ample room for innovation. None of the cores I have looked at are particularly small. I think a minimal-area core is an interesting design challenge. And of course, the sky is the limit in the high-frequency / high-IPC direction.
For me, instruction compatibility with the original 6502 is not very interesting or useful without also having clock cycle compatibility. Since improved IPC is one of your goals I would forget about the original and start with the 65C02 as a baseline. Get that working on some FPGA dev board before adding new instructions/features. There are many design trade-offs to consider for this seemingly simple (but definitely not) project. For starters, do you optimize for embedded or external RAM? Do you emphasize portability or optimize for a specific FPGA family?
If you are more interested in exploring instruction sets in simulation and less interested in ultimately building something these thoughts are probably not helpful. Maybe we find fun in the same things, maybe we don't. By all means, focus on what floats your boat.