Hello everyone,

I'm planning to build a somewhat portable 65C02 based system, and I have a couple of questions I'd like to ask.

First of all, what are all these different types of RAM? There is SRAM, NVSRAM, NVRAM, Asynchronous RAM, SDRAM, and all that. I am aware of their acronyms, and what the terms mean, but I can't seem to piece them together. Trying to see what they all were just made me more confused, and now I need someone to please explain me what is what and which ones I should use for my system.

I also need some help to determine how to run my display. I plan on using an ATMega controller to run the display, but I want it to be able to share system RAM (As opposed to a serial-style interface). What should I do to prevent some sort of reading conflict (ie, the ATMega wants to access the bus at the same time the 65C02 does). My design plans to be similar to Daryl Rictor's design with the ATMega (and the graphical LCD screen, see http://sbc.rictor.org/io/vid4.html, albeit my screen might be smaller).

I plan on using about 128 KB of RAM (bank switchable via a peripheral device), 128 KB of ROM (also bank switchable), a W65C02S running at somewhere between 6-10 MHz (depends on the RAM and ROM response time speeds I can get from what i can order), I will have a serial/COM interface for communications with my PC, and wish to be able to attach devices to it using the VIA/PIA.

Sorry if I sound arrogant or ignorant, I will admit to be liable to both (hey, I'm just human ). This is my first time attempting into making my own computer, but I do feel ready for it. Those little things are just fascinating, don't' you think so? Any help whatsoever would be appreciated, and sorry in advance if i am being redundant.

Thanks!

SRAM is the RAM type most commonly used with 6502 systems because of its simplicity (no DRAM management hardware is needed), its speed, the fact that it can easily be battery-backed, and it's quite affordable in the quantities typically used in 6502 systems.

The Apple II had the display access the RAM during phase 1 and the processor accessed it in phase 2; so both could run full speed at the same time without getting in each other's way.

Instead of bank-switching the memory, I would highly recommend using the 65816 instead. It's only about a dollar more (and you'll easily save the dollar in the support logic), and directly addresses up to 16MB of memory. Its registers can be switched to and from 16-bit mode on the fly which makes some programming jobs much easier than they are in 8-bit. It has a lot of extra instructions and addressing modes that make it much more conducive to multitasking, relocatable code, big stacks, etc. and running higher-level languages two or three times as fast as the 65c02 can at the same clock speed. I know it looks intimidating at first, but it really does make some programming jobs a lot easier. If you want to postpone using the new capabilites, you can initially use it in 6502 emulation mode, exactly as if it were a 6502. Or, you can put a few jumpers on your board so it will easily accommodate either processor.

You can use phase 1 clock to share video, without degrading the throughput of the CPU. My SBC-3 is using that approach.

You can also use wait-states to give the video engine priority over the CPU. I have not studied that method but I know it has been used.

I went back to one of my video threads because I remembered a poster who was using the ATM8 to control the 6502's clock and accessing RAM during phase 1.

See the post by Barnacle in this thread
viewtopic.php?t=187&start=0

You may want to contact him if he's still out there for more details.

Like Garth said, use SRAM. There is a 28 pin DIP .6" wide 62256 version. There's also a 28 pin dip, .3" wide, faster version from Cypress, the CY7C199. It doesn't use the JEDEC standard pinout like the 62256 does, but it does come in faster speeds.

These can use a 2-3v battery to retain memory when power is removed.

Are you wanting to stay with standard 74 series logic or is GAL or CPLD an option?

Good luck with your design... and keep us posted on your progress.

Daryl

First of all, thanks for the fast replies.

Well I was considering the 65816 as an option, but I felt taunted by the address and data bus being multiplexed. I'm sure I could probably use some 74 series logic to do that, as well as decode addresses.

If I understand well, the approach using the SBC-3 in order to let the processor and the video both use the RAM is as simple as this: let the video chip access the RAM on the low phase, the processor on high, the video on low, etc...

Thanks for clearing up on the RAM for me. SRAM it is then.

From what I understand as well, you must place capacitors as close to the chips' power supply pins as possible in order to reduce the noise generated by other circuitry. I also need a brief primer on how and when to use capacitors/resistors as well, as I understand what they do, but I don't know how to use them... I believe resistors are used (or not used) with IC's to maintain lines high or low depending on the circuit specifications, or to lower voltage between components, or to make current flow in a direction.

Thanks again, and sorry if I'm redundant. I often am.

It just takes a single 8-bit latch. That's it. If you don't want to use any more than 64K memory space, you don't even need that. You'll get get tons of benefits from using the '816. It is not necessary to latch, decode, or use the bank byte (the high eight bits of the 24-bit address). If you do use it, it's still much easier than using I/O bits to select banks like you were planning, and doing a block copy even from one bank to another only takes 7 clocks per byte which is much, much faster.

In digital work, you'll mostly only use resistors for passively pulling a line up or down, and most digital CMOS circuits won't even use that. I²C (a serial interface that allows communication with lots of ICs by way of only two wires) uses pull-up resistors like the PC keyboard interface. Then Dallas has their 1-Wire interface, also with a pull-up. These interfaces are nice for certain things, but are not nearly as fast as something like SPI which does not use resistors. Virtually the only time you'll put a resistor in series will be for something like controlling the current on LED indicators, or setting the viewing angle on an LCD. If you were to put a resistor in series with a digital line, the time constant formed with the resistance and the load capacitance would make it too slow.

For the capacitor question, see my posts at viewtopic.php?p=800

Yes, that is how SBC-3 is doing it. And yes, a 74AC573 transparent latch is all that's needed to capture the upper 8 address lines. SBC-3 also does that, using transparent latch circuits in the CPLD.

Daryl

First of all, thanks for the helpful information you've been giving me. I now understand why and how capacitors and resistors are used on circuits, and I now also understand how to create a timing circuit for the CPU (that was learned by reading a bit on the forums here, and a helpful couple of tips from the Internet).

I've set finally how much ROM, RAM and I/O devices I will have. I plan on having x2 6522's (VIA), x1 6551 (ACIA), as well as 128 KBytes of RAM and 128 KBytes or ROM. What I plan on doing for the ROM is having a 64KByte chunk that will contain the OS, and another 64KByte chunk that will allow the user to load his own program (in assembler); and for the RAM, I plan on having 4 of those 32 KByte chips together.

I've decided that I shall do my system addressing as follows:


000000-0000FF -> I/O
000100-01FFFF -> RAM
020000-03FFFF -> ROM
040000-FFFFFF -> Reserved/Unused

I've already made a list of my address logic, as follows(address lines 0-23):

Accessing I/O -> lines 8-23 must all be off!
RAM -> line 17 must be off, but at least 1 line from 8-16 must be on
ROM -> line 17 must be on

Now for a more detailed I/O description:

VIA #1: All lines 4-23 must be off
VIA #2: All lines 5-23 must be off, and line 4 must be on
ACIA: lines 6-23 must be off, and line 5 must be on

Now, the only problem is that I am afraid that if I add more 74 series logic, I will slow down the already slow EEPROM, and that this will force me to reduce the CPU speed. This is not a huge problem for me, but then I will also have to slow down the speed of the ATMega that will be controlling the video, and therefore make the video controller less efficient (maybe up to the point where you can see it drawing to the screen). Since I have decided I too will have a screen resolution of 320x240, I am wondering what performance impacts this may have.

I've done enough of these that I know from experience that "I've decided" is always tentative, and may keep changing. That's fine though, because you learn more about what's better as you go.

So, it looks like you decided to go for the '816? The '816 allows you to move direct page (DP) around, but on the '02 it will always be page 0, also called zero page (ZP), and you will have to have RAM there for some of the indirect addressing modes. There's no negotiating on that with the '02.

Next, you'll save some work and board space while getting more memory at the same time if you just go with a 512Kx8 SRAM instead of four 32Kx8's. You'll probably save money too. You definitely will by the time you consider the price of wire-wrap sockets. EPROMs come up to a megabyte or two.

Remember that the VIA and ACIA have two chip-select inputs, simplifying your addressing-decoding logic requirements and reducing the delays. Take advantage.

You need the RAM select to be gated by phase 2, but you don't need the ROM select gated by it. This gives the ROM longer to respond, which is good because the lowest (E)EPROM access times are longer than the lowest RAM access times. Do not gate the VIAs' and ACIA's chip-select lines with phase 2. Those have to be valid before phase 2 rises.

See my tips starting at viewtopic.php?t=342 .

How are you planning to handle the Reset vectors? As your memory map is, power-on reset will have RAM where the Reset vector is.

Will you be using the 65c02 or 65C816?

You still need to bank the ROM into bank-0 when booting up and handling interrupts, since all exceptions, traps, and interrupts will start execution there (the vectors are all 16-bits wide, and assume code resides in bank 0).

One idea I've been kicking around for the Kestrel was to have a signal, ROMEN, which when asserted, forced ROM to appear in the $00C000-$00FFFF range. When negated, RAM underneath it appeared. ROMEN would be a signal coming from a VIA chip, and which was forced-asserted whenever _RESET was asserted, thus guaranteeing the CPU would always be bootable.

After booting, the ROM could load data into RAM in $00C000-$00FFFF, turn off ROMEN, and then function with completely custom code. I have even kicked around the idea of a RORAM signal (Read-Only RAM), so that I can optionally treat the "kernel RAM" as if it were ROM by write-protecting it.

Another idea is to use the VP, VPA, and VDA lines to decode when a code or vector pull reference is made to bank 0, and redirect it to ROM. This would allow LDA and STA to continue to access RAM, while normal opcode and vector fetches occur from ROM.

Just a couple of ideas.

Yes, I am a person who often changes his mind. I always say things are definitive, but in fact I don't mean that to 100%. Just know that I usually think like this: if it must change, it will, and if it's fine the way it is, then it let it be.

Indeed, I have decided to go for the 65816. Ill save the 6502 for when I need to make a small embedded system to do something more invisible (like controlling the lights).

Oopsies, I forgot about the reset vectors and such. I'll just switch the ROM, RAM and I/O around, I don't have a huge preference on where they are situated, just as long as they are there.

One thing about the 512x8 Kb SRAM: I can't seem to find it in DIP format, only in TSOP and the such. Seeing as how the SBC-3 also uses that small format, I'm pretty sure they either don't make those sizes in DIP anymore, or just never really did.

In that case, how would I go to using one of those? (the pins are small!) I don't think I have the appropriate soldering equipment, although I can somehow arrange to get things from abroad.

The '816 doesn't require any more external parts than the '02 if you don't use more than the first 64K of memory space. An exception might be if you can get away with just a resistor and capacitor hung on the '02 for a clock source instead of using an external oscillator.

I have some 512Kx8 SRAMs here in DIPs. I even stacked four on a DIP header to get 2Mx8, with a 74AC139 stood on edge at the end to select the right chip. You can see the stack in this picture:



This board is actually two projects, with the five ICs at the right end being a circuit to let me use a VIA's serial port to put raster graphics on an analog oscilloscope. It was cool the first time I was able to put a paragraph of text on a totally analog 'scope! It uses the Z-axis input to turn the beam off and on.

Jameco has the 512Kx8 DIP SRAMs at here, so you know it's pretty basic stuff. I think I got mine at Debco for a lot less.

If you can go down to 3V, you can get 2Mx8, but those are all SMT.

Aries makes adapters so you can use SMT parts with DIP sockets. [Edit: Winslow ones are available at http://uk.rs-online.com/web/c/?searchTe ... ra=oss&r=t. Thanks Ed for the notice.] There are other manufacturers too, but stay away from Ironwood which is many times as expensive and no better. Soldering just takes a lot of flux and a lot of solder, but not a tiny iron. A 1/8" chisel tip will be fine since you won't solder just one pin at a time. To start, solder just the end pins on one side, just enough to hold the IC in place. Bridges are ok for now. Then solder down the other row of pins, using lots of flux and lots of solder. It may be all one huge solder bridge, but that's ok to start. Then you hold the board vertically and slowly run the soldering iron from top to bottom, re-melting all the solder on that side. The excess will stay on the iron, not the IC, and there will be no bridges. Now go back and do the first side which until now was only tacked. Clean off the flux, and it looks like it was done by machine. Perfect. It really is surprisingly easy.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I chose this part because I needed something that could handle a 40ns access time. The part Garth linked to is a 70ns part. Depending upon your design, it may work for you at 8MHz project. At 8MHz system clock, there's 62.5ns during each clock phase.

I had some trouble at first with the SOJ chip, but found that a lot of flux really helped, and you don't need expensive equipment to solder it. Check out my SMT lessons Learned post:

viewtopic.php?t=1228

Daryl

The Debco one is 55ns, but they seem to be temporarily out of stock. I see Digi-Key has Cypress 10ns 512Kx8 SRAM in a 36-lead SOJ which is not much harder to solder than the SOICs.

The Cypress SOJ is the part I'm using in SBC-3. It helps to have a PCB with solder mask layer to help prevent the solder bridges. My prototype SBC-3 Core didn't have a solder mask and the bridges were harder to eliminate.