Chromatix wrote:
The 2A03 has some built-in devices which live at relatively high addresses. It would be reasonable for the CPU to execute something other than what was on the data bus when reading from those devices.
So, does it mean everything is perfectly normal? Signals on A14 and A15 should look like that?
If so, I'd like to proceed with the next test, run some code from an EPROM and change state of one of the built-in outputs.
Then I'll try to use video controller: UA6538.
I also have few other question regarding schematic I use as a reference.
1) Why there is a filter on U1 (SRAM) CS line? It will cause significant delay in chip activation. C20 will be discharged slowly by R14, so the stope of the signal won't be steep. After deselecting CD line capacitor will be quickly charged again through D1. What is the reason of that? I always thought SRAM should be selected right away after setting its address on address lines...
2) Why there are C21 and C23 capacitors on DBE line of video chip?
3) How to test my device by toggling one ox the OUTx lines?