Take your cycle time (the inverse of your phase-2 frequency), subtract the address set-up time (tADS from the data sheet), and then subtract also the read data set-up time (tDSR also from the data sheet). You'll probably also have some address-decoding logic, so you'll have to subtract its guaranteed maximum propagation delay. You don't normally need any data buffers, but if you have them, they'll take extra too.
So for example, if you have a 14MHz WDC W65C02S and you're running it at 8MHz and 5V, your cycle time will be 125ns. From that, subtract the tADS which is 30ns max, and the tDSR which needs to be at least 10ns, and you get 85ns. Now let's say your address decoding takes a maximum of 25ns. That leaves you with 60ns for your ROM. Again, you don't normally need any data buffers, but if you have them, you'll have to subtract their delay as well, getting you down to approximately the very fastest of the common EPROMs or EEPROMs available, if you want it to be reliable.
It's highly unlikely that all of the parts will be at their worst guaranteed times, so with good design, you'll probably find that you can run the computer substancially faster than the data sheet numbers indicate-- but you can't count on it. If you're on the raggedy edge of it working, you might say, "It works great!", and then you find it doesn't work at all on a warmer day, since higher temperature slows it down. Lower power supply voltage will slow it down too. It would be good to increase the clock frequency until the computer starts having problems, just to feel for where the limit is, and then back it down a comfortable margin.
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