Hello everyone. I just registred so pretty new on this forums. Been reading some of the intresting discussion on them so I figured Id register.

Anyhow... Im thinking some of describing a 6502 using VHDL. Ive taken a quick look at some of the VHDL sources out there but Im one of them persons that wanna "fully" understand things and not "Ctrl+C/V" parts of code.

So...Ive started thinking how I should describe my 6502 compatible cpu.
I found a intresting article about describing some of the timing circuits inside the 6502. The article also included a decent block scheme of the inside of the 6502(supposedly coming from the real blueprints).

Gah now Im babbling.

Anyhow in my cpu Im having a state machine.
ABL/ABH can only be loaded during clk1='1'.

Data is loaded into the "Inpuut data latch" during clk2='1'.

Counter is Loaded(with either PC or PC+1[depending if I want it increased]) during clk2='1'.

ALU hold register is loaded during clk2='1' from ALU_out.



So basically all datapaths can only be controlled during clk='1' then it all idles until next clk='1'.

The state is also changed on the rising edge of clk.

Anyhow..this all makes sense to me. The only problem I have is really with the ALU.

For example(ADC instruction. Zero paged).
-------------------------------------------------
CLK='1': IR contains the opcode and describes what and how
many next states there will be for the effective adress
calculation.
CLK2='1': New data is fetched into the input latch(Zero page adress).

CLK='1': Connect input latch to ADL-buss and load ABL with data
from ADL.
Enable "grounding" of ADH-buss and load ABH with data
from ADH(0x00).
CLK2='1': New data is fetched from the input latch.

CLK='1' Connect input latch to ALU input B and load it.
Connect Accumulator to ALU input A(using SB-buss) and
load it. Enable ALU and make it output the SUM.
CLK2='1' ALU_hold register is loaded with the SUM.

CLK='1' Make ALU_hold register output its content to the SB buss
and load the data from the SB Buss to the accumulator.
CLK2='1' Load new opcode into instruction register.


Now...This is great it performs the ADC Zero paged with great sucess and all...
There's only one problem. It took the CPU 4 Clock cycles to perform it when it should only take 3.

What am i missing? Maybe Im totally lost in understand the 6502.

Thanks for all replies.


P.S. My explanation in how I think wasnt the best but...

I designed a 6502 in TTL. If I have a lot of time left, I'll build in real one day :)
Knowing that the ALU has to be used, I copy the contents of register A in the temporary latch for input A (as you call it) during the very first "CLK = '1'". During step 2 "CLK2 = '1'" the data is fed immediatly to the ALU. The moment CLK2 becomes '0', the result is stored in A again. You see, only three steps needed.

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