Bryan Parkoff wrote:
OK. I think that you misunderstand what my code means.
No, I understood your code crystal clear.
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I am not confused.
I was going to say that I never said that you were, but your response to me suggests that, in fact, you are. What I had written was that you
write in a confusing manner. I never claimed that you were confused.
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Now, I am trying to say why data bank register is incremented by X Index from 16-bit address bus on 65816.
followed by
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I am aware that data bank register is not modified
This is what I mean when I say you write in a confusing way. I would suggest that you consider your words more carefully. At least I know what you mean now.
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Is my explanation clear to you?
It is now, yes.
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It is a question why $FFFF wraps into $010000 on 65816.
Because it takes less hardware.
To implement wrap-around logic requires more gates, and offers no significant advantage in practice.
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I do not understand what you are trying to say the emulation?
If you engineer a computer around the 65816, you'll know that the chip has a pin called "E". This signal is true when the CPU is running in 6502-mode, and false when in native-mode. This allows
external logic to respond to the CPU's current operating mode, which could well include masking A23-A16 to all zeros if required (like the A20-gate on Intel-based PCs).
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No matter if emulation flag above processor status is set to 0 or 1 when temporary data bank register is modified into effective address. I suggest you to try to test on your 65816 machine and see it yourself.
I've engineered several computers around the 65816, and am working on another. I can assure you I'm extremely familiar with how the 65816 works, both from a software and a hardware perspective.
Thanks.