stebra wrote:
If someone is going to make a fast 65c02, why cannot they make it so it's 100% compatible ?!
Because the laws of physics prevents it. The faster the signals, the faster the slew, which means the higher the frequencies of RF it generates, which means the more adjacent traces act like receiving antennas.
I am willing to bet a slice of pizza that your problem is cross-talk on the bus, along with a slow slew rate on the phi-2 clock input. The WDC65C02 chip
MUST have 5ns or faster slew on phi-2. No exceptions. To do otherwise, even if you're running it at 1 cycle per second, will result in unpredictable CPU behavior. I know -- I learned this lesson the hard way.