Yes, a grid is what you want... more or less. More particularly, for any signal trace from A to B ("some pin" on one IC to "some pin" on some other IC), you ideally want a return path available which takes the same route as the signal path.

A grid is easy to design, and it makes multiple return paths available... which means any A-to-B signal path has an approximately matching return path nearby. The return path will have extra jigs and jogs because it's confined to the east-west and north-south lines of the grid. (With a ground plane, there are no unnecessary jigs and jogs because the return current is free to follow ANY possible path. The return current "wants" to hug the signal path. The closest hugging path is the most attractive path.)

The grid falls short of perfection because jigs and jogs won't match the signal path exactly. (Unless you're canny, and lay out the ground connections firstly... and only then route your Clock or other critical signals so they DO match exactly. )

If the signal path is diagonal, the ideal return path is also diagonal.

If the signal path is meandering, the ideal return path is also meandering.

Notice what we're seeing here. In this latter case a longer wire is actually better. Of course we prefer that both of those paths be short. But if there's a meandering signal path from A to B, and that route can't be improved, then a meandering ground path is better than a straight ground path from A to B. What's most important is for the return path to hug the signal path.

I'm gonna dodge that question for fear of getting confused myself! But what we're concerned about is high-frequency signals (like ringing), not DC. So, for purposes of this discussion I believe it's unhelpful to distinguish between pulling high and pulling low.

Also: where high-frequency signals are concerned, it's useful to view a capacitor as just a piece of wire (its capacitance means it has low impedance). That's simplifying slightly, as it also has some inductance. But on the question of having two grids -- one each for Gnd and Vcc -- IMO it's almost as good to just have one grid, with "pieces of wire" as local connect points for the grid that's absent.

(Hm, Garth just posted saying he considers the Vcc grid less critical but still very helpful. IOW, we agree it's better to have two grids, but differ on the question of how much better. I concede that caps with long leads, as used in this project, make comparatively poor "pieces of wire" and thus adding a Vcc grid may be very helpful. But where SMD caps are properly used, I'd say a single grid approach is more viable, and adding a second one won't make as much difference.)

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for the replies. I'm going to add vertical wires to form the proposed grid and see what influence it has.
A couple notes:
Power and ground is routed on the underside using soldered wire made for wire-wrapping.
Clock is coming from a 555 timer, but is buffered by some gates, and rising/falling edge are as fast as the rest of the signals.

We'll see how it goes.
Juan

So this would be one of the cards. I've added vertical wires, and additional ones here and there where I saw fit. Also most columns have an individual wire going to the backplane connector. Now the two remaining ones.
Juan

So this is something I'm not entirely (or at all :-)) clear on, then. I had thought that the connection between the ground and Vcc pins of an IC through a decoupling capacitor should be as short as possible. (Wikipedia says, "The longer the conductor between the capacitor and the device, the more inductance is present.") So it seems to me that the boards in this product are about as optimum as you can get (short of using axial-lead capacitors in the same way) because the caps go diagonally across the underside of the IC, rather than through the longer traces you'd need to put a cap beside the IC. Or were you talking about using SMD caps under ICs, effectively doing the axial-lead thing? What am I missing here? Some better way of using SMD caps that you can't do with through-hole parts?

_________________
Curt J. Sampson - github.com/0cjs

cjs:

To my understanding, the ideal case is smd caps as close as possible to the device and connected straight to a ground plane (which would have less inductance than the leads of a capacitor). In this case, as there is no ground plane, I think this is the way to go regarding those caps. Please correct me if I'm wrong.
Juan

My eyelid twitches when I see "as close as possible." I suspect we really mean don't have 10cm of wire that you don't need. Is there any meaningful difference between 1cm of wire and 1mm of wire, in this context? Of course one of those is ten times longer than the other, but the parasitics are surely very small in both cases.

I'll reply to several points at once.

Ed, you imply (and I agree) that one needs to know how much worrying is enough. Indeed, in the other thread I remarked, "There will always be one more tweak -- it's endless! -- so I don't wanna be obsessive." That did need to be said. Now we're left with a discussion involving certain principles, and it seems to me the phrase "as close as possible" is useful in explaining the ideal we strive for.

OK, great. Obviously I can't promise this'll resolve the symptom you were observing. But improving the ground distribution is not difficult, and may have benefits beyond what's involved in this immediate situation.

Also good. But I'll note in passing that the assignments on the backplane aren't optimal. The distance between a typical signal path and its return path would be smaller if the ground lines were assigned near the center of the backplane rather than at one end. I'm not suggesting you change that now, though.

That's right, and thanks for your comments. I guess I'm subconsciously assuming that SMD caps would be used in a project which also uses SMD IC's -- whose Gnd and Vcc pins are closer together, and this changes the situation. ATM I'm not able to be more concise -- perhaps I'll refine these thoughts later. This stuff is sometimes hard to think about, and always a challenge to explain.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It seems to be doing the business. Will provide more detail later, but clock edges look cleaner, and it executes successfully a little program I wrote in assembly that just counts to 256 by two's on a 1 MHz clock.
Thanks everyone.
Juan

Ok, so that's fine. I was just worried I was missing something special about SMD, but if the rule is just "minimum length between Vcc and the decoupling cap, and between the cap and GND, then I can apply that to through-hole, SMD, or whatever I'm using. (On a PC board, for example, I might have an SMD cap underneath the DIP IC, but is pretty near exactly the same effect as using an axial-lead cap soldered to the underside of the board: very short length of conductor+cap between the pins.)

_________________
Curt J. Sampson - github.com/0cjs

There is still some ringing on the clock (see attached, clock is light blue), but I'm not sure how much is coming from the circuit itself, or if it has anything to do with probing artifacts. It seems to work every single time now. I also attached a screenshot from a logic analyzer connected to the accumulator, showing it counting by two's as programmed. I also fixed an issue with bus conflicts during reset.
I'll try to test the RAM today.
Juan

When making PCB layouts with GND polygons, it would be best to place the SMD capacitor as close as possible to the VCC pin of a chip.

Mouser has axial 100nF capacitors, like Vishay A104K15X7RF5UAA (0.09€), but IMHO they would just take less PCB space without really improving the situation.

Andrew Holme took a creative approach to distributing GND and VCC on the PCBs in his Mark 1 FORTH Computer.

Something you could try is adding a 2.2uF tantalum capacitor to the power supply of every 4 TTL chips or such and to every EPROM.

The ringing on the screen doesn't look too bad, of course the probeheads of your scope also have some capacitance,
so the ringing might be slightly worse than seen on the screen if no probeheads are attached to the signal.
// I just had to mention this in case you might encounter a situation where your design only works with the probeheads attached to the circuitry.

Nice progress fo far, good luck with the RAM.

I don't have any tantalums on my parts bin, but will put some on order just in case. I am aware of probe capacitance. Fortunately, seems to work with and without probes.

I have (lightly) tested the RAM by writing and reading to/from it and also calling subroutines so the stack is used. Seems to work as expected.
Also made a frame for the CPU (right) and peripherals (left) to sit more comfortably. First card on the left holds RAM, ROM, clock and reset. I will use a shorter section of the IDE cable and cut down the rest, but as of now comes in handy for moving things around.

I tried interfacing to an LCD display as in here: http://www.6502.org/mini-projects/optrexlcd/lcd.htm, but no luck yet. Will try using a microcontroller to get the hang of it first.
I am thinking of adding a couple 7-segment displays so I can get some output information beyond looking at the accumulator (good think about a CPU like this is that I can stop it at any time and have a look at every register)

And I also have to think about address decoding and such.

Juan

I've got the LCD working (sort of). I had the data bus reversed...
Temporarily, writing to any of the spare 16K I have writes to the LCD, just for testing.

I'm using the as65 assembler, (I had it setup for Klauss test suite). Below is the code I've written:
I suppose this is the official documentation: http://www.obelisk.me.uk/dev65/as65.html, but for example using .ORG as stated there gives me errors, but using org does not. Is there any further documentation?

In addition, I expected it to fill empty addresses with FF, so that for example the reset vectors land in the correct place. Is there something that I'm missing? Thanks.
Juan



And this is the listing:

Hmm that dw doesn't seem to have put anything into the listing. Try another one after it? Or a comment? (Or check that there's a line-end at the end of your last line, maybe.)

Adding .end after the code seems to have fixed it. Thanks
Juan