I have put together an SPI interface that can connect directly to the 65C02/65C816 bus.
I would like to know how many people are interested in using this interface. If there is
enough interest, then I'll continue with testing and let you know how it progresses.
thanks!
Daryl
65SPI
It uses a 44-pin (PLCC) Xilinx XC9572 CPLD. It is currently in prototype. I have not tested it yet.
It had the typical 65xx bus connections:
/RES, PHI2, R/W, /CS, A0, A1, /IRQ
The SPI side has MOSI, MISO,SCLK, 8 Slave Select Lines (SS0-SS7)
The MOSI, SCLK, and Slave Select pins are tristated when SPI is disabled
Here is a preview of the features:
Operates as an SPI master
SCLK has an 8 bit programmable divider
range is 1/2 PHI2 down to 1/512 PHI2
Mode 0,1,2,3 supported
Shifts MSB first
8-bit Slave select register with 8 Slave Select outputs.
External decoding can yield up to 255 addresses.
Direct decoding yields 8 devices
The register addresses are decoded like this:
Code:
A1 A0 R/W Function
0 - 0 : R SPI Data in and clear FIN & IRQ flags
0 - 0 : W SPI data out, enable shifting and set BSY
0 - 1 : R Status Register, See below
0 - 1 : W Control Register, see below
1 - 0 : R SPI Clock divisor
1 - 0 : W SPI Clock divisor
1 - 1 : R Slave Select register
1 - 1 : W Slave Select register
Control register has these functions
ENA - SPI Enable - disable tristates SPI pins and disables shifting
IER - Enables IRQ when shifting is completed
CPOL - selects mode
CPHA - selects mode
** /RES clears all 4 Control registers.
Status Register reports these flags:
IRQ - active IRQ - reading Data Register clears this flag
IER - Interrupt Enable Register
ENA - SPI interface enabled
FIN - Finished shifting current byte, cleared when Data Register is read - for polled interface
BSY - Active while shifting is in progress, cleared when shifting is completed - for polled interface
CPOL - reflects status of CPOL register
CPHA - reflects status of CPHA register
Your Feedback is welcome