And finally, some signs on life
Last night I put the CPU in place, and, byte by byte (I´m also working on a small app to upload a whole image at once, of course
), uploaded this code to RAM
Code:
*=$FFE0
lda #$00 // A9 00
sta $0300 // 8D 00 03
jmp $FFE5 // 4C E5 FF
*=$FFFC "Reset Vector"
.word $FFE0
And it kinda works...
Somehow the byte at FFE1 is being rewritten. Just that one, everything else stays the same, and value at $0300 is properly stored. As it seems to work, I'm thinking I'm causing some incorrect write to RAM when I ask the Arduino to take back the control of the bus. My sequence is as follows.
On power-up. BE is pulled Low, and the Nano takes control of the bus. Via the shift registers for the address buses, directly for R/W and the data bus.
Then, the Nano writes to the ram. As it's driving the address bus, all the addressing logic is in effect. I can write $0000-$7FFF and $C000-$FFFF. I could also write to the peripherals, but they're not in place yet.
When I´m done writing the RAM this happens:
1.- RESET the 6502 (And the 6522, as they share /RES)
2.- Release R/W from the Nano (Set it as INPUT)
3.- Release the Data Bus (Set all bits as INPUT)
4.- Pull BE HIGH. This also puts the shift registers into HIGH-Z mode, so the address bus is released too
5.- After a small delay, RESET is pulled high, and the 6502 starts running.
To halt execution and return control to the nano:
1.- Pull BE low. So the 6502 disconnects from the buses. At this point, the shift registers drive the bus again. Data and R/W are floating right now.
2.- Set R/W and Data as outputs in the NANO.
As the (very tiny) code I'm uploading seems to run fine, I think the spurious write is happening when the Nano takes control of the bus again. This was not something I planned, and won't be needing in the future when I had a proper output from the SBC (The LCD). I'll try some more complex code today, before pulling out the logic analyzer
By the way, I spotted one small flaw in the design. Again, I've been kinda lucky.
I didn't take into account the difference between 65C22N and 65C22S, regarding it's IRQ output. I was aware of it, but it didn't pop into my mind at design time. So both /IRQs from the 6522 and 6526 are connected to the CPU. But then I failed to put the pull-up resistor in the schematic!
Why have I been lucky? Well... I wanted the CIA and VIA interrupts to be independent, so CIA /IRQ is connected to CPU /IRQ, while VIA /IRQ is connected to /NMI. So no conflict between the open collector nature of the CIA, and the totem-pole /IRQ of the VIA (I have a 65C22S, again, lucky I guess... didn't even check it when I bought it!)
In the end, I just need to add a pullup resistor to the /IRQ line. It could've been much much worse.
Today... the 65C22 will be added... and that will be it for now. I don't have the '245 buffer yet, and who knows when I'll be able to get it
Cheers!